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PIC32MX3XX/4XX Data Sheet
High-Performance, General Purpose and USB, 32-bit Flash Microcontrollers
(c) 2011 Microchip Technology Inc.
DS61143H
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
ISBN: 978-1-61341-149-0
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS61143H-page 2
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
High-Performance, General Purpose and USB 32-bit Flash Microcontrollers
High-Performance 32-bit RISC CPU:
* MIPS32(R) M4K(R) 32-bit core with 5-stage pipeline * 80 MHz maximum frequency * 1.56 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state Flash access * Single-cycle multiply and high-performance divide unit * MIPS16e(R) mode for up to 40% smaller code size * Two sets of 32 core register files (32-bit) to reduce interrupt latency * Prefetch Cache module to speed execution from Flash * Separate PLLs for CPU and USB clocks * Two I2CTM modules * Two UART modules with: - RS-232, RS-485 and LIN support - IrDA(R) with on-chip hardware encoder and decoder * Up to two SPI modules * Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data and up to 16 address lines * Hardware Real-Time Clock and Calendar (RTCC) * Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) * Five capture inputs * Five compare/PWM outputs * Five external interrupt pins * High-Speed I/O pins capable of toggling at up to 80 MHz * High-current sink/source (18 mA/18 mA) on all I/O pins * Configurable open-drain output on digital I/O pins
Microcontroller Features:
* Operating temperature range of -40C to +105C * Operating voltage range of 2.3V to 3.6V * 32K to 512K Flash memory (plus an additional 12 KB of boot Flash) * 8K to 32K SRAM memory * Pin-compatible with most PIC24/dsPIC(R) DSC devices * Multiple power management modes * Multiple interrupt vectors with individually programmable priority * Fail-Safe Clock Monitor Mode * Configurable Watchdog Timer with on-chip Low-Power RC Oscillator for reliable operation
Debug Features:
* Two programming and debugging Interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire MIPS(R) standard enhanced JTAG interface * Unintrusive hardware-based instruction trace * IEEE Standard 1149.2-compatible (JTAG) boundary scan
Peripheral Features:
* Atomic SET, CLEAR and INVERT operation on select peripheral registers * Up to 4-channel hardware DMA with automatic data size detection * USB 2.0-compliant full-speed device and On-The-Go (OTG) controller * USB has a dedicated DMA channel * 3 MHz to 25 MHz crystal oscillator * Internal 8 MHz and 32 kHz oscillators
Analog Features:
* Up to 16-channel 10-bit Analog-to-Digital Converter: - 1000 ksps conversion rate - Conversion available during Sleep, Idle * Two Analog Comparators
(c) 2011 Microchip Technology Inc.
DS61143H-page 3
PIC32MX3XX/4XX
TABLE 1: PIC32MX GENERAL PURPOSE - FEATURES
GENERAL PURPOSE
Timers/Capture/Compare Program Memory (KB) Programmable DMA Channels
Data Memory (KB)
EUART/SPI/I2CTM
10-bit ADC (ch)
Comparators
Packages(2)
PMP/PSP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
VREG
Trace
Device
PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H PIC32MX320F128L PIC32MX340F128L
64 64 64 64 64 64 100 121 100 121 100
PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT BG PT BG PT BG PT BG
40 80 80 80 80 80 80 80
32 + 12(1) 64 + 12
(1)
8 16 16 32 32 32 16 32
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
0 0 0 4 4 4 0 4
Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No
2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2 2/2/2
16 16 16 16 16 16 16 16
2 2 2 2 2 2 2 2
Yes Yes Yes Yes Yes Yes Yes Yes
128 + 12(1) 128 + 12(1) 256 + 12(1) 512 + 12
(1)
128 + 12(1) 128 + 12(1)
PIC32MX360F256L PIC32MX360F512L Legend: Note 1: 2: PT = TQFP
121 100 121
80 80
256 + 12(1) 512 + 12(1) BG = XBGA
32 32
5/5/5 5/5/5
4 4
Yes Yes Yes Yes
2/2/2 2/2/2
16 16
2 2
Yes Yes
MR = QFN
This device features 12 KB Boot Flash memory. See Legend for an explanation of the acronyms. See Section 30.0 "Packaging Information" for details.
DS61143H-page 4
(c) 2011 Microchip Technology Inc.
JTAG
Pins
MHz
PIC32MX3XX/4XX
TABLE 2: PIC32MX USB - FEATURES
USB
Timers/Capture/Compare Program Memory (KB) Dedicated USB DMA Channels Programmable DMA Channels
Data Memory (KB)
EUART/SPI/I2CTM
10-bit ADC (ch)
Comparators
Packages(2)
PMP/PSP Yes Yes Yes Yes Yes Yes Yes
VREG
Trace
Device
PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L Legend: Note 1: 2: PT = TQFP
64 64 64 64 100 121 100 121 100 121
PT, MR PT, MR PT, MR PT, MR PT BG PT BG PT BG MR = QFN
40 80 80 80 80 80 80
32 + 12(1) 128 + 12
(1)
8 32 32 32 32 32 32
5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5
0 4 4 4 4 4 4
2 2 2 2 2 2 2
Yes Yes Yes Yes Yes
No No No No No
2/1/2 2/1/2 2/1/2 2/1/2 2/2/2 2/2/2 2/2/2
16 16 16 16 16 16 16
2 2 2 2 2 2 2
Yes Yes Yes Yes Yes Yes Yes
256 + 12(1) 512 + 12(1)
128 + 12(1) 256 + 12(1) 512 + 12(1) BG = XBGA
Yes Yes Yes Yes
This device features 12 KB Boot Flash memory. See Legend for an explanation of the acronyms. See Section 30.0 "Packaging Information" for details.
(c) 2011 Microchip Technology Inc.
DS61143H-page 5
JTAG
Pins
MHz
PIC32MX3XX/4XX
Pin Diagrams
64-Pin QFN (General Purpose)
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 U1CTS/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H
DS61143H-page 6
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Pin Diagrams (Continued)
64-Pin TQFP (General Purpose)
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIC32MX320F032H PIC32MX320F064H PIC32MX320F128H PIC32MX340F128H PIC32MX340F256H PIC32MX340F512H
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/INT4/RD11 IC3/PMCS2/PMA15/INT3/RD10 U1CTS/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3
(c) 2011 Microchip Technology Inc.
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61143H-page 7
PIC32MX3XX/4XX
Pin Diagrams (Continued)
100-Pin TQFP (General Purpose)
= Pins are up to 5V tolerant
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/PMA14/RD11 IC3/PMCS2/PMA15/RD10 IC2/RD9 RTCC/IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3
DS61143H-page 8
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD U1CTS/CN20/RD14 U1RTS/CN21/RD15 U2RX/PMA9/CN17/RF4 U2TX/PMA8/CN18/RF5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Pin Diagrams (Continued)
121-Pin XBGA(1)
PIC32MX320F128L PIC32MX340F128L PIC32MX360F256L PIC32MX360F512L = Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
A
RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1
B
NC
RG15
RE2
RE1
RA7
RF0
VCORE/ VCAP
RD5
RD3
VSS
RC14
C
RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11
D
RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10
E
RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14
F
MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15
G
RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4
H
RB5 RB4 VSS VDD NC VDD NC RF7 RF6 RG2 RA2
J
RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3
K
RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2
L
RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5
Note 1: Refer to Table 3 for full pin names.
(c) 2011 Microchip Technology Inc.
DS61143H-page 9
PIC32MX3XX/4XX
TABLE 3:
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 PMD10/RF1 ENVREG VSS IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 PMD11/RF0 VCAP/VCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) PMD14/CN15/RD6 PMD13/CN19/RD13 OC1/RD0 No Connect (NC) IC3/PMCS2/PMA15/RD10 T5CK/RC4 T4CK/RC3 SCK2/PMA5/CN8/RG6 T3CK/RC2 VDD PMD9/RG1 VSS
PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND PIC32MX360F512L DEVICES
Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 INT4/RA15 RTCC/IC1/RD8 IC2/RD9 INT3/RA14 MCLR SDO2/PMA3/CN10/RG8 SS2/PMA2/CN11/RG9 SDI2/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 INT1/RE8 INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) SDI1/RF7 SCK1/INT0/RF6 SCL1/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/SS1/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/PMA12/RB11 TCK/RA1 AN12/PMA11/RB12 No Connect (NC) No Connect (NC) SDO1/RF8 SDA1/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/PMA6/RA10 Full Pin Name
DS61143H-page 10
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 3:
Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) U2CTS/RF12 AN14/PMALH/PMA1/RB14 VDD U1RTS/CN21/RD15 U1TX/RF3 U1RX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/PMA7/RA9
PIN NAMES: PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F128L, AND PIC32MX360F512L DEVICES (CONTINUED)
Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 U2RTS/RF13 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 CN20/U1CTS/RD14 U2RX/PMA9/CN17/RF4 U2TX/PMA8/CN18/RF5 Full Pin Name
(c) 2011 Microchip Technology Inc.
DS61143H-page 11
PIC32MX3XX/4XX
Pin Diagrams (Continued)
64-Pin QFN (USB)
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 U1TX/OC4/RD3 U1RX/OC3/RD2 U1RTS/OC2/RD1
PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12//RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS61143H-page 12
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Pin Diagrams (Continued)
64-Pin TQFP (USB)
= Pins are up to 5V tolerant
PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 U1TX/OC4/RD3 U1RX/OC3/RD2 U1RTS/OC2/RD1
SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3
PIC32MX420F032H PIC32MX440F128H PIC32MX440F256H PIC32MX440F512H
(c) 2011 Microchip Technology Inc.
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12//RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 SDA2/U2RX/PMA9/CN17/RF4 SCL2/U2TX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61143H-page 13
PIC32MX3XX/4XX
Pin Diagrams (Continued)
100-Pin TQFP (USB)
= Pins are up to 5V tolerant
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 PMD10/RF1 PMD11/RF0 ENVREG VCAP/VCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1
RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2/PMA5/CN8/RG6 SDI2/PMA4/CN9/RG7 SDO2/PMA3/CN10/RG8 MCLR SS2/PMA2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS U1TX/RF8 U1RX/RF2 USBID/RF3
PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD U1CTS/CN20/RD14 U1RTS/CN21/RD15 U2RX/PMA9/CN17/RF4 U2TX/PMA8/CN18/RF5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DS61143H-page 14
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Pin Diagrams (Continued)
121-Pin XBGA(1)
PIC32MX440F128L PIC32MX460F256L PIC32MX460F512L = Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
A
RE4 RE3 RG13 RE0 RG0 RF1 ENVREG VSS RD12 RD2 RD1
B
NC
RG15
RE2
RE1
RA7
RF0
VCORE/ VCAP
RD5
RD3
VSS
RC14
C
RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11
D
RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10
E
RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14
F
MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15
G
RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4
H
RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2
J
RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3
K
RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2
L
RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5
Note 1: Refer to Table 4 for full pin names.
(c) 2011 Microchip Technology Inc.
DS61143H-page 15
PIC32MX3XX/4XX
TABLE 4:
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 PMD10/RF1 ENVREG VSS IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 PMD11/RF0 VCAP/VCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) PMD14/CN15/RD6 CN19/PMD13/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 SCK2/PMA5/CN8/RG6 T3CK/RC2 VDD PMD9/RG1 VSS
PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES
Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 SDA1/INT4/RA15 RTCC/IC1/RD8 SS1/IC2/RD9 SCL1/INT3/RA14 MCLR SDO2/PMA3/CN10/RG8 SS2/PMA2/CN11/RG9 SDI2/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) Vdd OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 INT1/RE8 INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/PMA12/RB11 TCK/RA1 AN12/PMA11/RB12 No Connect (NC) No Connect (NC) U1TX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/PMA6/RA10 Full Pin Name
DS61143H-page 16
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4:
Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) U2CTS/RF12 AN14/PMALH/PMA1/RB14 VDD U1RTS/CN21/RD15 USBID/RF3 U1RX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/PMA7/RA9
PIN NAMES: PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES (CONTINUED)
Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 U2RTS/RF13 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 U1CTS/CN20/RD14 U2RX/PMA9/CN17/RF4 U2TX/PMA8/CN18/RF5 Full Pin Name
(c) 2011 Microchip Technology Inc.
DS61143H-page 17
PIC32MX3XX/4XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 21 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 31 3.0 CPU............................................................................................................................................................................................ 37 4.0 Memory Organization ................................................................................................................................................................. 43 5.0 Flash Program Memory .............................................................................................................................................................. 85 6.0 Resets ........................................................................................................................................................................................ 87 7.0 Interrupt Controller ..................................................................................................................................................................... 89 8.0 Oscillator Configuration .............................................................................................................................................................. 93 9.0 Prefetch Cache........................................................................................................................................................................... 95 10.0 Direct Memory Access (DMA) Controller .................................................................................................................................. 97 11.0 USB On-The-Go (OTG).............................................................................................................................................................. 99 12.0 I/O Ports ................................................................................................................................................................................... 101 13.0 Timer1 ...................................................................................................................................................................................... 103 14.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 105 15.0 Input Capture............................................................................................................................................................................ 107 16.0 Output Compare....................................................................................................................................................................... 109 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 111 18.0 Inter-Integrated CircuitTM (I2CTM) .............................................................................................................................................. 113 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 115 20.0 Parallel Master Port (PMP) ...................................................................................................................................................... 119 21.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 121 22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 123 23.0 Comparator .............................................................................................................................................................................. 125 24.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 127 25.0 Power-Saving Features ........................................................................................................................................................... 129 26.0 Special Features ...................................................................................................................................................................... 131 27.0 Instruction Set .......................................................................................................................................................................... 141 28.0 Development Support............................................................................................................................................................... 147 29.0 Electrical Characteristics .......................................................................................................................................................... 151 30.0 Packaging Information.............................................................................................................................................................. 191 Index ................................................................................................................................................................................................. 209
DS61143H-page 18
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2011 Microchip Technology Inc.
DS61143H-page 19
PIC32MX3XX/4XX
NOTES:
DS61143H-page 20
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
1.0 DEVICE OVERVIEW
This document contains device-specific information for the PIC32MX3XX/4XX devices. Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX3XX/4XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 1-1:
OSC2/CLKO OSC1/CLKI
BLOCK DIAGRAM(1,2)
VCORE/VCAP OSC/SOSC Oscillators FRC/LPRC Oscillators PLL DIVIDERS PLL-USB USBCLK Timing Generation SYSCLK PBCLK Precision Band Gap Reference ENVREG Voltage Regulator
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
VDD, VSS MCLR
CN1-22 Peripheral Bus Clocked by SYSCLK Timer1-5 PORTA Priority Interrupt Controller ICD 32 INT Peripheral Bus Clocked by PBCLK USB PORTC EJTAG DMAC
PORTB
JTAG BSCAN
PWM OC1-5
IC1-5
MIPS32(R) M4K(R) CPU Core PORTD 32 PORTE Bus Matrix PORTF 32 PORTG 32 32 IS 32 DS 32 32 32 32
SPI1,2
I2C1,2 32 PMP 10-bit ADC
Prefetch Module
Data RAM
Peripheral Bridge UART1,2
128 128-bit wide Program Flash Memory Note 1: 2: Flash Controller
RTCC Comparators
Some features are not available on all device variants. BOR functionality is provided when the on-board voltage regulator is enabled.
(c) 2011 Microchip Technology Inc.
DS61143H-page 21
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS
Pin Number(1) Pin Type I I I I I I I I I I I I I I I I I O Buffer Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog ST/CMOS External clock source input. Always associated with OSC1 pin function. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Description
64-pin 100-pin QFN/TQFP TQFP 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 39 40 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 63 64
121-pin XBGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 F9 F11
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 CLKI CLKO
Analog input channels.
OSC1 OSC2
39 40
63 64
F9 F11
I I/O
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. -- Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI SOSCO
47 48
73 74
C10 B11
I O
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. -- 32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
DS61143H-page 22
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O I I I I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- -- -- -- -- ST ST ST ST Output Compare Fault A Input. Output Compare output 1. Output Compare output 2 Output Compare output 3. Output Compare output 4. Output Compare output 5. Output Compare Fault B Input. External interrupt 0. External interrupt 1. External interrupt 2. Capture inputs 1-5. Description
64-pin 100-pin QFN/TQFP TQFP 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 -- -- -- 42 43 44 45 52 17 46 49 50 51 52 30 35,46 42 43 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70 71 79 26 72 76 77 78 81 44 55,72 18 19
121-pin XBGA B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 E9 E10 D11 C11 A9 L1 D9 A11 A10 B9 C8 L8 H9,D9 61 62
CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2
Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
(c) 2011 Microchip Technology Inc.
DS61143H-page 23
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTC is a bidirectional I/O port. PORTB is a bidirectional I/O port. External interrupt 3. External interrupt 4. PORTA is a bidirectional I/O port. Description
64-pin 100-pin QFN/TQFP TQFP 44 45 -- -- -- -- -- -- -- -- -- -- -- -- 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 -- -- -- -- 39 47 48 40 66 67 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64
121-pin XBGA E11 E8 G3 J6 H11 G10 G11 G9 C5 B5 L2 K3 E11 E8 K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 D1 E4 E2 E1 F9 C10 B11 F11
INT3 INT4 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
DS61143H-page 24
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTF is a bidirectional I/O port. PORTE is a bidirectional I/O port. Description
64-pin 100-pin QFN/TQFP TQFP 46 49 50 51 52 53 54 55 42 43 44 45 -- -- -- -- 60 61 62 63 64 1 2 3 -- -- 58 59 34 33 31 32 35 -- -- -- -- 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 55 54 53 40 39
121-pin XBGA D9 A11 A10 B9 C8 B8 D7 C7 E9 E10 D11 C11 A9 D8 L9 K9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 B6 A6 K11 K10 L10 L11 H9 H8 J10 K6 L6
RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF12 RF13
PORTD is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
(c) 2011 Microchip Technology Inc.
DS61143H-page 25
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I O I O I O I O I/O I O I/O I/O I O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST -- ST -- ST -- ST -- ST ST -- ST ST ST -- ST ST ST ST ST Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. PORTG input pins. Description
64-pin 100-pin QFN/TQFP TQFP -- -- 4 5 6 8 -- -- -- -- 37 36 48 -- -- -- -- 43 35, 49 34, 50 33, 51 21 29 31 32 35 34 33 14 4 5 6 8 37, 44 36, 43 32 31 90 89 10 11 12 14 96 97 95 1 57 56 74 6 7 8 9 47 48 52 51, 53 40 39 49 50 55, 70 9, 54 53, 72 23, 69 10 11 12 14 57, 66 56, 67 58 59
121-pin XBGA A5 E6 E3 F4 F2 F3 C3 A3 C4 B2 H10 J11 B11 D1 E4 E2 E1 L9 K9 K11 J10, K10 K6 L6 L10 L11 D11, H9 E1, H8 D9, J10 E10, J2 E3 F4 F2 F3 E11, H10 E8, J11 H11 G10
RG0 RG1 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RG2 RG3 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 SCL1 SDA1 SCL2 SDA2
PORTG is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
DS61143H-page 26
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I I I O O I I O I I O I I O I/O I/O O O O O O O O O O O O O O O O O Buffer Type ST ST ST -- -- Analog Analog Analog Analog Analog -- Analog Analog -- TTL/ST TTL/ST -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Parallel Master Port Chip Select 1 Strobe. Parallel Master Port Chip Select 2 Strobe. Description
64-pin 100-pin QFN/TQFP TQFP 23 27 28 24 42 15 16 23 12 11 21 14 13 22 30 29 8 6 5 4 16 22 32 31 28 27 24 23 45 44 45 44 17 38 60 61 68 28 29 34 21 20 32 23 22 33 44 43 14 12 11 10 29 28 50 49 42 41 35 34 71 70 71 70
121-pin XBGA G3 J6 G11 G9 E9 L2 K3 L5 H2 H1 K4 J2 J1 L4 L8 K7 F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C11 D11
TMS TCK TDI TDO RTCC CVREFCVREF+ CVREFOUT C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2
JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Real-Time Clock Alarm Output. Comparator Voltage Reference (low). Comparator Voltage Reference (high). Comparator Voltage Reference Output. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (De-multiplexed Master Modes).
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
(c) 2011 Microchip Technology Inc.
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PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I P O I/O I/O I I O O O O O I/O I Buffer Type TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST -- -- -- -- Analog -- -- Analog Analog ST ST -- -- -- -- -- ST ST Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Address Latch Enable low-byte (Multiplexed Master modes). Parallel Master Port Address Latch Enable high-byte (Multiplexed Master modes). USB Bus Power Monitor. USB Internal Transceiver Supply. If the USB module is not used, this pin must be connected to VDD. USB Host and OTG Bus Power Control Output. USB D+. USB D-. USB OTG ID Detect. Enable for On-Chip Voltage Regulator. Trace Clock. Trace Data Bits 0-3. Description
64-pin 100-pin QFN/TQFP TQFP 60 61 62 63 64 1 2 3 -- -- -- -- -- -- -- -- 53 52 30 29 34 35 11 37 36 33 57 -- -- -- -- -- 16 15 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 82 81 44 43 54 55 20 57 56 51 86 91 97 96 95 92 25 24
121-pin XBGA A4 B4 B3 A2 A1 D3 C1 D2 A5 E6 A6 B6 A9 D8 D7 C7 B8 C8 L8 K7 H8 H9 H1 H10 J11 K10 A7 C5 A3 C3 C4 B5 K2 K1
PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMRD PMWR PMALL PMALH VBUS VUSB VBUSON D+ DUSBID ENVREG TRCLK TRD0 TRD1 TRD2 TRD3 PGED1 PGEC1
Parallel Master Port Data (De-multiplexed Master mode) or Address/Data (Multiplexed Master modes).
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
DS61143H-page 28
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PIC32MX3XX/4XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1) Pin Type I/O I I/P P P P Buffer Type ST ST ST P P -- Description
64-pin 100-pin QFN/TQFP TQFP 18 17 7 19 20 27 26 13 30 31
121-pin XBGA J3 L1 F1 J4 L3 C2, C9, E5, F8, G5, H4, H6, K8 B7 A8, B10, D4, D5, E7, F10, F5, G6, G7, H3 K3 L2
PGED2 PGEC2 MCLR AVDD AVSS VDD
Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins.
10, 26, 38 2, 16, 37, 46, 62
VCORE/ VCAP Vss
56 9, 25, 41
85 15, 36, 45, 65, 75
P P
-- --
Capacitor for Internal Voltage Regulator. Ground reference for logic and I/O pins.
VREF+ VREF-
16 15
29 28
I I
Analog Analog
Analog voltage reference (high) input. Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the "Pin Diagrams" section for device pin availability.
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PIC32MX3XX/4XX
NOTES:
DS61143H-page 30
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PIC32MX3XX/4XX
2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS
2.2 Decoupling Capacitors
The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: Recommendation of 0.1 F (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. * Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 F in parallel with 0.001 F. * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
2.1
Basic Connection Requirements
Getting started with the PIC32MX3XX/4XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: * All VDD and VSS pins (see Section 2.2 "Decoupling Capacitors") * All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 "Decoupling Capacitors") * VCAP/VCORE (see Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VCORE)") * MCLR pin (see Section 2.4 "Master Clear (MCLR) Pin") * PGECx/PGEDx pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSC1 and OSC2 pins when external oscillator source is used (see Section 2.8 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of ADC use and ADC voltage reference source.
(c) 2011 Microchip Technology Inc.
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PIC32MX3XX/4XX
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
0.1 F Ceramic CBP VDD VSS
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device functions: * Device Reset * Device Programming and Debugging Pulling The MCLR pin low generates a device reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin.
VDD R R1
MCLR VCAP/VCORE
CEFC
C PIC32MX
VSS VDD VDD VSS AVDD 0.1 F Ceramic CBP 0.1 F Ceramic CBP AVSS VDD 0.1 F Ceramic CBP VSS
0.1 F Ceramic CBP
10
2.2.1
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 F to 47 F. This capacitor should be located as close to the device as possible.
FIGURE 2-2:
EXAMPLE OF MCLR PIN CONNECTIONS
VDD R R1 MCLR JP C PIC32MX
2.3
2.3.1
Capacitor on Internal Voltage Regulator (VCAP/VCORE)
INTERNAL REGULATOR MODE
A low-ESR (< 1 Ohm) capacitor is required on the VCAP/VCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 29.0 "Electrical Characteristics" for additional information on CEFC specifications. This mode is enabled by connecting the ENVREG pin to VDD.
Note 1:
R 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1 470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. The capacitor can be sized to prevent unintentional resets from brief glitches or to extend the device reset period during POR.
2:
2.3.2
EXTERNAL REGULATOR MODE
3:
In this mode the core voltage is supplied externally through the VCORE/VCAP pin. A low-ESR capacitor of 10 F is recommended on the VCAP/VCORE pin. This mode is enabled by grounding the ENVREG pin. The placement of this capacitor should be close to the VCAP/VCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 26.3 "On-Chip Voltage Regulator" for details.
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PIC32MX3XX/4XX
2.5 ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the "Communication Channel Select" (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB(R) ICD 2, MPLAB ICD 3 or MPLAB REAL ICETM. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. * "MPLAB(R) ICD 2 In-Circuit Debugger User's Guide" DS51331 * "Using MPLAB(R) ICD 2" (poster) DS51265 * "MPLAB(R) ICD 2 Design Advisory" DS51566 * "Using MPLAB(R) ICD 3" (poster) DS51765 * "MPLAB(R) ICD 3 Design Advisory" DS51764 * "MPLAB(R) REAL ICETM In-Circuit Debugger User's Guide" DS51616 * "Using MPLAB(R) REAL ICETM" (poster) DS51749 Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements.
2.7
Trace
The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector.
2.8
External Oscillator Pins
Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3.
2.6
JTAG
The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
FIGURE 2-3:
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Oscillator Secondary Guard Trace
Guard Ring
Main Oscillator
(c) 2011 Microchip Technology Inc.
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PIC32MX3XX/4XX
2.9 Configuration of Analog and Digital Pins During ICSP Operations 2.10 Unused I/Os
Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternately, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input.
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analogto-Digital input pins (ANx) as "digital" pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the Analogto-Digital pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain Analog-toDigital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all Analog-to-Digital pins being recognized as analog input pins, resulting in the port value being read as a logic `0', which may affect user application functionality.
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PIC32MX3XX/4XX
2.11 Referenced Sources
This device data sheet is based on the following individual chapters of the "PIC32 Family Reference Manual". These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX460F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. * * * * * * * * * * * * * * * * * * * * * * * * * * Section 1. "Introduction" (DS61127) Section 2. "CPU" (DS61113) Section 3. "Memory Organization" (DS61115) Section 4. "Prefetch Cache" (DS61119) Section 5. "Flash Program Memory" (DS61121) Section 6. "Oscillator Configuration" (DS61112) Section 7. "Resets" (DS61118) Section 8. "Interrupt Controller" (DS61108) Section 9. "Watchdog Timer and Power-up Timer" (DS61114) Section 10. "Power-Saving Features" (DS61130) Section 12. "I/O Ports" (DS61120) Section 13. "Parallel Master Port (PMP)" (DS61128) Section 14. "Timers" (DS61105) Section 15. "Input Capture" (DS61122) Section 16. "Output Compare" (DS61111) Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS61104) Section 19. "Comparator" (DS61110) Section 20. "Comparator Voltage Reference (CVREF)" (DS61109) Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS61107) Section 23. "Serial Peripheral Interface (SPI)" (DS61106) Section 24. "Inter-Integrated CircuitTM (I2CTM)" (DS61116) Section 27. "USB On-The-Go (OTG)" (DS61126) Section 29. "Real-Time Clock and Calendar (RTCC)" (DS61125) Section 31. "Direct Memory Access (DMA) Controller" (DS61117) Section 32. "Configuration" (DS61124) Section 33. "Programming and Diagnostics" (DS61129)
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NOTES:
DS61143H-page 36
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PIC32MX3XX/4XX
3.0 CPU
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. "CPU" (DS61113) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32(R) M4K(R) Processor Core are available at: www.mips.com/products/cores/ 32-64-bit-cores/mips32-m4k/. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The MIPS32(R) M4K(R) Processor Core is the heart of the PIC32MX3XX/4XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16e(R) Code Compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 34 clock latency (dividend (rs) sign extension-dependent) Power Control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG Debug and Instruction Trace - Support for single stepping - Virtual instruction and data address/value - breakpoints - PC tracing with trace compression
*
* *
*
3.1
Features
*
* 5-stage pipeline * 32-bit Address and Data Paths * MIPS32 Enhanced Architecture (Release 2) - Multiply-Accumulate and Multiply-Subtract Instructions - Targeted Multiply Instruction - Zero/One Detect Instructions - WAIT Instruction - Conditional Move Instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base
*
FIGURE 3-1: CPU
MIPS(R) M4K(R) BLOCK DIAGRAM
EJTAG MDU Trace TAP Execution Core (RF/ALU/Shift) Off-Chip Debug I/F Dual Bus I/F Bus Matrix
DS61143H-page 37
Trace I/F
FMT
Bus Interface
System Coprocessor
Power Mgmt.
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
3.2 Architecture Overview
3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The MIPS32(R) M4K(R) Processor Core contains several logic blocks working together in parallel, providing an efficient high performance computing engine. The following blocks are included with the core: * Execution Unit * Multiply/Divide Unit (MDU) * System Control Coprocessor (CP0) * Fixed Mapping Translation (FMT) * Dual Internal Bus interfaces * Power Management * MIPS16e Support * Enhanced JTAG (EJTAG) Controller The MIPS32(R) M4K(R) Processor Core includes a multiply/divide unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the integer unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (`32' of 32x16) represents the rs operand. The second number (`16' of 32x16) represents the rt operand. The PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16bit-wide rs, 15 iterations are skipped, and for a 24-bitwide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks.
3.2.1
EXECUTION UNIT
The MIPS32(R) M4K(R) Processor Core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit general purpose registers used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: * 32-bit adder used for calculating the data address * Address unit for calculating the next instruction address * Logic for branch determination and branch target address calculation * Load aligner * Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results * Leading Zero/One detect unit for implementing the CLZ and CLO instructions * Arithmetic Logic Unit (ALU) for performing bitwise logical operations * Shifter and Store Aligner
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TABLE 3-1: MIPS(R) M4K(R) PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the general purpose register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction, required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, multiply-add (MADD) and multiply-subtract (MSUB), are used to perform the multiplyaccumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32
the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms.
3.2.3
SYSTEM CONTROL COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor's diagnostics capability, the operating modes (kernel, user and debug), and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2.
TABLE 3-2:
COPROCESSOR 0 REGISTERS
Function Reserved Enables access via the RDHWR instruction to selected hardware registers Reports the address for the most recent address-related exception Processor cycle count Reserved Timer interrupt control Processor status and control Interrupt system status and control Shadow register set status and control Provides mapping from vectored interrupt to a shadow set Cause of last general exception Program counter at last exception Processor identification and revision Exception vector base register Configuration register Configuration register 1 Configuration register 2 Configuration register 3
Register Register Number Name 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3
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TABLE 3-2: COPROCESSOR 0 REGISTERS (CONTINUED)
Function Reserved Debug control and exception status Program counter at last debug exception Reserved Program counter at last error Debug handler scratchpad register Register Register Number Name 17-22 23 24 25-29 30 31 Note 1: 2: Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2)
Registers used in exception processing. Registers used during debug.
Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 shows the exception types in order of priority.
TABLE 3-3:
Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
Description Assertion MCLR or a Power-on Reset (POR) EJTAG Debug Single Step EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the EjtagBrk bit in the ECR register Assertion of NMI signal Assertion of unmasked hardware or software interrupt signal EJTAG debug hardware instruction break matched Fetch address alignment error Fetch reference to protected address Instruction fetch bus error EJTAG Breakpoint (execution of SDBBP instruction) Execution of SYSCALL instruction Execution of BREAK instruction Execution of a Reserved Instruction Execution of a coprocessor instruction for a coprocessor that is not enabled Execution of a CorExtend instruction when CorExtend is not enabled Execution of an arithmetic instruction that overflowed Execution of a trap (when trap condition is true) EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value) Load address alignment error Load reference to protected address Store address alignment error Store to protected address Load or store bus error EJTAG data hardware breakpoint matched in load data compare
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PIC32MX3XX/4XX
3.3 Power Management 3.4 EJTAG Debug Support
The MIPS32(R) M4K(R) Processor Core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. The MIPS32(R) M4K(R) Processor Core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard user mode and kernel modes of operation, the core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define what registers are selected and how they are used.
3.3.1
INSTRUCTION-CONTROLLED POWER MANAGEMENT
The mechanism for invoking power-down mode is through execution of the WAIT instruction. For more information on power management, see Section 25.0 "Power-Saving Features".
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the PIC32MX3XX/4XX family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated-clocks to reduce this dynamic power consumption.
(c) 2011 Microchip Technology Inc.
DS61143H-page 41
PIC32MX3XX/4XX
NOTES:
DS61143H-page 42
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
4.0 MEMORY ORGANIZATION
4.1
* * * * * * * *
Key Features
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 3. "Memory Organization" (DS61115) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX3XX/4XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions including program, data memory, SFRs and Configuration registers reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX3XX/4XX to execute from data memory.
32-bit native data width Separate User and Kernel mode address space Flexible program Flash memory partitioning Flexible data RAM partitioning for data and program space Separate boot Flash memory for protected code Robust bus exception handling to intercept runaway code Simple memory mapping with Fixed Mapping Translation (FMT) unit Cacheable and non-cacheable address regions
4.2
PIC32MX3XX/4XX Memory Layout
PIC32MX3XX/4XX microcontrollers implement two address spaces: Virtual and Physical. All hardware resources such as program memory, data memory and peripherals are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by peripherals such as DMA and Flash controller that access memory independently of CPU.
(c) 2011 Microchip Technology Inc.
DS61143H-page 43
PIC32MX3XX/4XX
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX320F032H AND PIC32MX420F032H DEVICES(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD008000 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 0xA0001FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D008000 0x9D007FFF Program Flash(2) 0x9D000000 0x80002000 0x80001FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00002000 0x00001FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D008000 0x1D007FFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).
DS61143H-page 44
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX320F064H DEVICE(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D010000 0x9D00FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM
(2)
Physical Memory Map 0xFFFFFFFF
Reserved Device Configuration Registers
Reserved
Reserved
Reserved
KSEG1
SFRs
Reserved
0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).
(c) 2011 Microchip Technology Inc.
DS61143H-page 45
PIC32MX3XX/4XX
FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX320F128H AND PIC32MX320F128L DEVICES(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).
DS61143H-page 46
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX340F128H, PIC32MX340F128L, PIC32MX440F128H AND PIC32MX440F128L DEVICES(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).
(c) 2011 Microchip Technology Inc.
DS61143H-page 47
PIC32MX3XX/4XX
FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX340F256H, PIC32MX360F256L, PIC32MX440F256H AND PIC32MX460F256L DEVICES(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D040000 0x1D03FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).
DS61143H-page 48
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX340F512H, PIC32MX360F512L, PIC32MX440F512H AND PIC32MX460F512L DEVICES(1)
Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF
Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. "Memory Organization" (DS61115)) and can be changed by initialization code provided by end-user development tools (refer to the specific development tool documentation for information).
(c) 2011 Microchip Technology Inc.
DS61143H-page 49
DS61143H-page 50 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-1:
Virtual Address (BF88_#) Bit Range Register Name
BUS MATRIX REGISTERS MAP
Bits All Resets
0042 -- 0000 0000 -- -- -- -- -- -- 0000 0000 -- -- -- -- -- -- 0000 0000 xxxx BMXDRMSZ<31:0> 15:0 31:16 15:0 31:16 BMXPFMSZ<31:0> 15:0 31:16 BMXBOOTSZ<31:0> 15:0 3000 xxxx 0000 -- -- -- -- -- -- -- -- -- -- -- -- BMXPUPBA<19:16> xxxx 0000 0000 xxxx
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2000
BMX CON(1) BMX DKPBA(1) BMX DUDBA(1) BMX DUPBA(1) BMX DRMSZ BMX PUPBA(1) BMX PFMSZ BMX BOOTSZ
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- --
-- -- --
-- -- --
-- -- --
-- -- --
BMXCHEDMA -- --
-- -- --
-- -- --
-- -- --
-- BMXWSDRM --
-- -- --
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F -- -- -- -- -- BMXARB<2:0> --
2010
BMXDKPBA<15:0> -- -- -- -- -- -- -- -- -- --
2020
BMXDUDBA<15:0> -- -- -- -- -- -- -- -- -- --
2030
BMXDUPBA<15:0>
2040
2050
BMXPUPBA<15:0>
2060
2070
Legend: Note 1:
x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET, and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-2:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF -- SPI2TXIF OC5IE OC1IE -- SPI2TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC5IF IC1IF -- SPI2EIF IC5IE IC1IE -- SPI2EIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5IF T1IF -- CMP2IF T5IE T1IE -- CMP2IE INT4IF INT0IF DMA3IF CMP1IF INT4IE INT0IE DMA3IE CMP1IE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1IP<2:0> CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U2IP<2:0> DMA2IP<2:0> DMA0IP<2:0> -- -- OC4IF CS1IF DMA2IF PMPIF OC4IE CS1IE DMA2IE PMPIE IC4IF CS0IF DMA1IF AD1IF IC4IE CS0IE DMA1IE AD1IE T4IF CTIF DMA0IF CNIF T4IE CTIE DMA0IE CNIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 51
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 1010 1020 1030 1040 1060 1070 1090 10A0 10B0 10C0 10D0 10E0 10F0 1100 1110 1120 1140
INTCON INTSTAT(2) IPTMR IFS0 IFS1 IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- --
-- -- -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- SRIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> I2C1MIF INT3IF -- RTCCIF I2C1MIE INT3IE -- RTCCIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1SIF OC3IF -- FSCMIF I2C1SIE OC3IE -- FSCMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1BIF IC3IF -- I2C2MIF I2C1BIE IC3IE -- I2C2MIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U1TXIF T3IF -- I2C2SIF U1TXIE T3IE -- I2C2SIE U1RXIF INT2IF -- I2C2BIF U1RXIE INT2IE -- I2C2BIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> SPI2IP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> -- -- U1EIF OC2IF -- U2TXIF U1EIE OC2IE -- U2TXIE SPI1RXIF IC2IF USBIF U2RXIF IC2IE USBIE U2RXIE SPI1TXIF T2IF FCEIF U2EIF T2IE FCEIE U2EIE SPI1EIF INT1IF -- SPI2RXIF SPI1EIE INT1IE -- SPI2RXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
SPI1RXIE SPI1TXIE
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> SPI2IS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> -- --
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1IS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U2IS<1:0> DMA2IS<1:0> DMA0IS<1:0> -- --
PIC32MX3XX/4XX
Legend: Note 1: 2:
15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers.
Virtual Address (BF88_#)
DS61143H-page 52 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-3:
INTERRUPT REGISTERS MAP FOR PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY(1)
Bits All Resets Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SS0 0000 -- -- -- MVEC -- TPC<2:0> -- -- -- INT4EP INT3EP INT2EP INT1EP INT0EP 0000 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 1010 INTSTAT(2) 15:0 -- -- -- -- -- SRIPL<2:0> -- -- VEC<5:0> 0000 31:16 0000 1020 IPTMR IPTMR<31:0> 15:0 0000 31:16 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000 1030 IFS0 15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000 -- -- -- -- -- -- -- FCEIF -- -- -- -- DMA3IF DMA2IF DMA1IF DMA0IF 0000 31:16 1040 IFS1 15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 31:16 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000 1060 IEC0 15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000 31:16 -- -- -- -- -- -- -- FCEIE -- -- -- -- DMA3IE DMA2IE DMA1IE DMA0IE 0000 1070 IEC1 -- -- -- -- -- SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 15:0 RTCCIE FSCMIE I2C2MIE 31:16 -- -- -- INT0IP<2:0> INT0IS<1:0> -- -- -- CS1IP<2:0> CS1IS<1:0> 0000 1090 IPC0 -- -- -- CS0IP<2:0> CS0IS<1:0> -- -- -- CTIP<2:0> CTIS<1:0> 0000 15:0 31:16 -- -- -- INT1IP<2:0> INT1IS<1:0> -- -- -- OC1IP<2:0> OC1IS<1:0> 0000 10A0 IPC1 15:0 -- -- -- IC1IP<2:0> IC1IS<1:0> -- -- -- T1IP<2:0> T1IS<1:0> 0000 31:16 -- -- -- INT2IP<2:0> INT2IS<1:0> -- -- -- OC2IP<2:0> OC2IS<1:0> 0000 10B0 IPC2 -- -- -- IC2IP<2:0> IC2IS<1:0> -- -- -- T2IP<2:0> T2IS<1:0> 0000 15:0 31:16 -- -- -- INT3IP<2:0> INT3IS<1:0> -- -- -- OC3IP<2:0> OC3IS<1:0> 0000 10C0 IPC3 -- -- -- IC3IP<2:0> IC3IS<1:0> -- -- -- T3IP<2:0> T3IS<1:0> 0000 15:0 31:16 -- -- -- INT4IP<2:0> INT4IS<1:0> -- -- -- OC4IP<2:0> OC4IS<1:0> 0000 10D0 IPC4 15:0 -- -- -- IC4IP<2:0> IC4IS<1:0> -- -- -- T4IP<2:0> T4IS<1:0> 0000 31:16 -- -- -- SPI1IP<2:0> SPI1IS<1:0> -- -- -- OC5IP<2:0> OC5IS<1:0> 0000 10E0 IPC5 -- -- -- IC5IP<2:0> IC5IS<1:0> -- -- -- T5IP<2:0> T5IS<1:0> 0000 15:0 31:16 -- -- -- AD1IP<2:0> AD1IS<1:0> -- -- -- CNIP<2:0> CNIS<1:0> 0000 10F0 IPC6 -- -- -- I2C1IP<2:0> I2C1IS<1:0> -- -- -- U1IP<2:0> U1IS<1:0> 0000 15:0 31:16 -- -- -- SPI2IP<2:0> SPI2IS<1:0> -- -- -- CMP2IP<2:0> CMP2IS<1:0> 0000 1100 IPC7 15:0 -- -- -- CMP1IP<2:0> CMP1IS<1:0> -- -- -- PMPIP<2:0> PMPIS<1:0> 0000 31:16 -- -- -- RTCCIP<2:0> RTCCIS<1:0> -- -- -- FSCMIP<2:0> FSCMIS<1:0> 0000 1110 IPC8 -- -- -- I2C2IP<2:0> I2C2IS<1:0> -- -- -- U2IP<2:0> U2IS<1:0> 0000 15:0 31:16 -- -- -- DMA3IP<2:0> DMA3IS<1:0> -- -- -- DMA2IP<2:0> DMA2IS<1:0> 0000 1120 IPC9 -- -- -- DMA1IP<2:0> DMA1IS<1:0> -- -- -- DMA0IP<2:0> DMA0IS<1:0> 0000 15:0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 31:16 1140 IPC11 15:0 -- -- -- -- -- -- -- -- -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 Legend: x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. 2: This register does not have associated CLR, SET, and INV registers. 1000 INTCON
(c) 2011 Microchip Technology Inc. DS61143H-page 53
TABLE 4-4:
Virtual Address (BF88_#)
INTERRUPT REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H AND PIC32MX320F128L DEVICES ONLY(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF -- SPI2TXIF OC5IE OC1IE -- SPI2TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC5IF IC1IF -- SPI2EIF IC5IE IC1IE -- SPI2EIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5IF T1IF -- CMP2IF T5IE T1IE -- CMP2IE INT4IF INT0IF -- CMP1IF INT4IE INT0IE -- CMP1IE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1IP<2:0> CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U2IP<2:0> -- -- OC4IF CS1IF -- PMPIF OC4IE CS1IE -- PMPIE IC4IF CS0IF -- AD1IF IC4IE CS0IE -- AD1IE T4IF CTIF -- CNIF T4IE CTIE -- CNIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 1010 1020 1030 1040 1060 1070 1090 10A0 10B0 10C0 10D0 10E0 10F0 1100 1110 1140
INTCON INTSTAT(2) IPTMR IFS0 IFS1 IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC11
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- --
-- -- -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- SRIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> I2C1MIF INT3IF -- RTCCIF I2C1MIE INT3IE -- RTCCIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1SIF OC3IF -- FSCMIF I2C1SIE OC3IE -- FSCMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1BIF IC3IF -- I2C2MIF I2C1BIE IC3IE -- I2C2MIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U1TXIF T3IF -- I2C2SIF U1TXIE T3IE -- -- U1RXIF INT2IF -- I2C2BIF U1RXIE INT2IE -- -- INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> SPI1IP<2:0> IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> SPI2IP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> -- -- U1EIF OC2IF -- U2TXIF U1EIE OC2IE -- -- SPI1RXIF IC2IF -- U2RXIF IC2IE -- -- SPI1TXIF T2IF FCEIF U2EIF T2IE FCEIE -- SPI1EIF INT1IF -- SPI2RXIF SPI1EIE INT1IE -- SPI2RXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
SPI1RXIE SPI1TXIE
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> SPI1IS<1:0> IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> SPI2IS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> -- --
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1IS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U2IS<1:0> -- --
PIC32MX3XX/4XX
Legend: Note 1: 2:
-- -- -- -- -- -- -- -- -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers.
TABLE 4-5:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTERS MAP FOR PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1)
Bits All Resets
DS61143H-page 54 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000
INTCON
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- --
-- -- -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- SRIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
0000 0000 0000 0000 0000 0000
1010 INTSTAT(2) 1020 1030 1040 1060 1070 1090 10A0 10B0 10C0 10D0 10E0 10F0 1100 1110 1120 1140 Legend: Note 1: 2: IPTMR IFS0 IFS1 IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11
VEC<5:0>
IPTMR<31:0> I2C1MIF INT3IF -- RTCCIF I2C1MIE INT3IE -- RTCCIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1SIF OC3IF -- FSCMIF I2C1SIE OC3IE -- FSCMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1BIF IC3IF -- I2C2MIF I2C1BIE IC3IE -- I2C2MIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U1TXIF T3IF -- I2C2SIF U1TXIE T3IE -- I2C2SIE U1RXIF INT2IF -- I2C2BIF U1RXIE INT2IE -- I2C2BIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> -- IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> SPI2IP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> DMA3IP<2:0> DMA1IP<2:0> -- -- -- U1EIF OC2IF -- U2TXIF U1EIE OC2IE -- U2TXIE -- IC2IF USBIF U2RXIF -- IC2IE USBIE U2RXIE -- T2IF FCEIF U2EIF -- T2IE FCEIE U2EIE -- INT1IF -- SPI2RXIF -- INT1IE -- SPI2RXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC5IF OC1IF -- SPI2TXIF OC5IE OC1IE -- SPI2TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC5IF IC1IF -- SPI2EIF IC5IE IC1IE -- SPI2EIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5IF T1IF -- CMP2IF T5IE T1IE -- CMP2IE INT4IF INT0IF DMA3IF CMP1IF INT4IE INT0IE DMA3IE CMP1IE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1IP<2:0> CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U2IP<2:0> DMA2IP<2:0> DMA0IP<2:0> -- -- OC4IF CS1IF DMA2IF PMPIF OC4IE CS1IE DMA2IE PMPIE IC4IF CS0IF DMA1IF AD1IF IC4IE CS0IE DMA1IE AD1IE T4IF CTIF DMA0IF CNIF T4IE CTIE DMA0IE CNIE
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> -- -- IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> SPI2IS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> DMA3IS<1:0> DMA1IS<1:0> -- --
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1IS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U2IS<1:0> DMA2IS<1:0> DMA0IS<1:0> -- --
15:0 -- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers.
TABLE 4-6:
Virtual Address (BF88_#) Bit Range Register Name
INTERRUPT REGISTERS MAP FOR THE PIC32MX420F032H DEVICE ONLY(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 OC5IF OC1IF -- SPI2TXIF OC5IE OC1IE -- SPI2TXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IC5IF IC1IF -- SPI2EIF IC5IE IC1IE -- SPI2EIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- T5IF T1IF -- CMP2IF T5IE T1IE -- CMP2IE INT4IF INT0IF -- CMP1IF INT4IE INT0IE -- CMP1IE CS1IP<2:0> CTIP<2:0> OC1IP<2:0> T1IP<2:0> OC2IP<2:0> T2IP<2:0> OC3IP<2:0> T3IP<2:0> OC4IP<2:0> T4IP<2:0> OC5IP<2:0> T5IP<2:0> CNIP<2:0> U1IP<2:0> CMP2IP<2:0> PMPIP<2:0> FSCMIP<2:0> U2IP<2:0> -- -- OC4IF CS1IF -- PMPIF OC4IE CS1IE -- PMPIE IC4IF CS0IF -- AD1IF IC4IE CS0IE -- AD1IE T4IF CTIF -- CNIF T4IE CTIE -- CNIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 55
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
1000 1010 1020 1030 1040 1060 1070 1090 10A0 10B0 10C0 10D0 10E0 10F0 1100 1110 1140
INTCON INTSTAT(2) IPTMR IFS0 IFS1 IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC11
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- --
-- -- -- --
-- -- -- --
-- MVEC -- --
-- -- -- --
-- --
-- TPC<2:0> -- SRIPL<2:0>
-- --
-- -- -- --
-- -- -- --
-- -- --
-- INT4EP --
-- INT3EP --
-- INT2EP --
-- INT1EP --
SS0 INT0EP --
VEC<5:0>
IPTMR<31:0> I2C1MIF INT3IF -- RTCCIF I2C1MIE INT3IE -- RTCCIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1SIF OC3IF -- FSCMIF I2C1SIE OC3IE -- FSCMIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I2C1BIF IC3IF -- I2C2MIF I2C1BIE IC3IE -- I2C2MIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U1TXIF T3IF -- I2C2SIF U1TXIE T3IE -- I2C2SIE U1RXIF INT2IF -- I2C2BIF U1RXIE INT2IE -- I2C2BIE INT0IP<2:0> CS0IP<2:0> INT1IP<2:0> IC1IP<2:0> INT2IP<2:0> IC2IP<2:0> INT3IP<2:0> IC3IP<2:0> INT4IP<2:0> IC4IP<2:0> -- IC5IP<2:0> AD1IP<2:0> I2C1IP<2:0> SPI2IP<2:0> CMP1IP<2:0> RTCCIP<2:0> I2C2IP<2:0> -- -- -- U1EIF OC2IF -- U2TXIF U1EIE OC2IE -- U2TXIE -- IC2IF USBIF U2RXIF -- IC2IE USBIE U2RXIE -- T2IF FCEIF U2EIF -- T2IE FCEIE U2EIE -- INT1IF -- SPI2RXIF -- INT1IE -- SPI2RXIE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
INT0IS<1:0> CS0IS<1:0> INT1IS<1:0> IC1IS<1:0> INT2IS<1:0> IC2IS<1:0> INT3IS<1:0> IC3IS<1:0> INT4IS<1:0> IC4IS<1:0> -- -- IC5IS<1:0> AD1IS<1:0> I2C1IS<1:0> SPI2IS<1:0> CMP1IS<1:0> RTCCIS<1:0> I2C2IS<1:0> -- --
CS1IS<1:0> CTIS<1:0> OC1IS<1:0> T1IS<1:0> OC2IS<1:0> T2IS<1:0> OC3IS<1:0> T3IS<1:0> OC4IS<1:0> T4IS<1:0> OC5IS<1:0> T5IS<1:0> CNIS<1:0> U1IS<1:0> CMP2IS<1:0> PMPIS<1:0> FSCMIS<1:0> U2IS<1:0> -- --
PIC32MX3XX/4XX
Legend: Note 1: 2:
-- -- -- USBIP<2:0> USBIS<1:0> -- -- -- FCEIP<2:0> FCEIS<1:0> 0000 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers.
TABLE 4-7:
Virtual Address (BF80_#) Bit Range Register Name
TIMER1-5 REGISTERS MAP(1)
Bits All Resets
DS61143H-page 56 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0600 0610 0620 0800 0810 0820 0A00 0A10 0A20 0C00 0C10 0C20 0E00 0E10 0E20
T1CON TMR1 PR1 T2CON TMR2 PR2 T3CON TMR3 PR3 T4CON TMR4 PR4 T5CON TMR5 PR5
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON -- -- -- ON -- -- -- ON -- -- -- ON -- -- -- ON -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- SIDL -- -- -- SIDL -- -- -- SIDL -- -- -- SIDL -- -- -- SIDL -- --
-- TWDIS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TWIP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TGATE -- -- -- TGATE -- -- -- TGATE -- -- -- TGATE -- -- -- TGATE -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- -- -- TCKPS<2:0> -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- T32 -- -- -- -- -- -- -- T32 -- -- -- -- -- --
-- TSYNC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TCS -- -- -- TCS(2) -- -- -- TCS(2) -- -- -- TCS(2) -- -- -- TCS(2) -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000
TCKPS<1:0>
TMR1<15:0> PR1<15:0>
TMR2<15:0> PR2<15:0>
TMR3<15:0> PR3<15:0>
TMR4<15:0> PR4<15:0>
TMR5<15:0>
Legend: Note 1: 2:
15:0 PR5<15:0> FFFF x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This bit is not available on 64-pin devices.
(c) 2011 Microchip Technology Inc. DS61143H-page 57
TABLE 4-8:
Virtual Address (BF80_#) Bit Range Register Name
INPUT CAPTURE1-5 REGISTERS MAP
Bits All Resets
0000 0000 xxxx xxxx -- ON -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx -- ON -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx -- ON -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx -- ON -- -- -- SIDL -- -- -- -- -- -- -- FEDGE -- C32 -- ICTMR -- ICI<1:0> -- -- ICOV -- ICBNE -- -- ICM<2:0> -- 0000 0000 xxxx xxxx
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2000 2010 2200 2210 2400 2410 2600 2610 2800 2810
IC1CON(1) IC1BUF IC2CON(1) IC2BUF IC3CON(1) IC3BUF IC4CON(1) IC4BUF IC5CON(1) IC5BUF
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON
-- --
-- SIDL
-- --
-- --
-- --
-- FEDGE
-- C32
-- ICTMR
-- ICI<1:0>
--
-- ICOV
-- ICBNE
--
-- ICM<2:0>
--
IC1BUF<31:0>
IC2BUF<31:0>
IC3BUF<31:0>
IC4BUF<31:0>
Legend: Note 1:
IC5BUF<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
PIC32MX3XX/4XX
TABLE 4-9:
Virtual Address (BF80_#) Bit Range Register Name
OUTPUT COMPARE1-5 REGISTERS MAP(1)
Bits All Resets
DS61143H-page 58 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000 OC1CON 3010 3020 OC1R OC1RS
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON
-- --
-- SIDL
-- --
-- --
-- --
-- --
-- --
-- --
-- --
-- OC32
-- OCFLT
-- OCTSEL
--
-- OCM<2:0>
--
0000 0000 xxxx xxxx
OC1R<31:0> OC1RS<31:0> -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
xxxx xxxx 0000 0000 xxxx xxxx
3200 OC2CON 3210 3220 OC2R OC2RS
OC2R<31:0> OC2RS<31:0> -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
xxxx xxxx 0000 0000 xxxx xxxx
3400 OC3CON 3410 3420 OC3R OC3RS
OC3R<31:0> OC3RS<31:0> -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
xxxx xxxx 0000 0000 xxxx xxxx
3600 OC4CON 3610 3620 OC4R OC4RS
OC4R<31:0> OC4RS<31:0> -- ON -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OC32 -- OCFLT -- OCTSEL -- -- OCM<2:0> --
xxxx xxxx 0000 0000 xxxx xxxx
3800 OC5CON 3810 3820 OC5R OC5RS
OC5R<31:0>
Legend: Note 1:
xxxx OC5RS<31:0> 15:0 xxxx x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-10:
Virtual Address (BF80_#) Bit Range Register Name
I2C1-2 REGISTERS MAP(1)
Bits All Resets
0000 1000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- TRSTAT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SCLREL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STRICT -- -- -- -- -- -- -- -- -- -- -- -- A10M -- BCL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DISSLW -- GCSTAT -- -- -- -- -- -- SMEN -- ADD10 -- -- GCEN -- IWCOL -- -- STREN -- I2COV -- -- ACKDT -- D/A -- -- -- -- ADD<9:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MSK<9:0> I2C2BRG<11:0> I2CT2DATA<7:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADD<9:0> -- -- -- -- -- -- -- -- ACKEN -- P -- -- -- -- -- -- RCEN -- S -- -- -- -- -- -- PEN -- R/W -- -- -- -- -- -- RSEN -- RBF -- -- -- -- -- -- SEN -- TBF -- MSK<9:0> I2C1BRG<11:0> I2CT1DATA<7:0> I2CR1DATA<7:0> 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 59
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5000 5010
I2C1CON I2C1STAT
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON -- ACKSTAT --
-- -- -- TRSTAT --
-- SIDL -- -- --
-- SCLREL -- -- --
-- STRICT -- -- --
-- A10M -- BCL --
-- DISSLW -- GCSTAT --
-- SMEN -- ADD10 --
-- GCEN -- IWCOL --
-- STREN -- I2COV --
-- ACKDT -- D/A --
-- ACKEN -- P --
-- RCEN -- S --
-- PEN -- R/W --
-- RSEN -- RBF --
-- SEN -- TBF --
5020
I2C1ADD
5030 5040
I2C1MSK I2C1BRG I2C1TRN I2C1RCV I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C2BRG I2C2TRN I2C2RCV
-- -- -- -- -- -- -- -- -- ON -- ACKSTAT -- -- -- -- -- -- -- -- --
5050 5260 5200 5210 5220 5230 5240
PIC32MX3XX/4XX
5250 5260
Legend: Note 1:
15:0 -- -- -- -- -- -- -- -- I2CR2DATA<7:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
DS61143H-page 60 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-11:
Virtual Address (BF80_#) Register Name
UART1-2 REGISTERS MAP
Bits All Resets
0000 0000 0000 FERR -- -- -- -- OERR -- -- -- -- URXDA -- -- -- -- STSEL URXDA -- -- -- 0110 0000 0000 0000 0000 0000 0000 -- LPBACK -- ABAUD ADDEN -- -- -- -- RXINV RIDLE -- -- -- -- BRGH PERR -- -- -- 0000 0000 0000 FERR -- -- -- OERR -- -- -- 0110 0000 0000 0000 0000 0000 0000
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6000 U1MODE(1) 6010 6020 6030 6040 U1STA(1) U1TXREG U1RXREG U1BRG
(1)
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON -- -- -- -- -- -- -- ON -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- SIDL -- UTXINV -- -- -- -- -- -- SIDL -- UTXINV -- -- -- -- --
-- IREN -- URXEN -- -- -- -- -- -- IREN -- URXEN -- -- -- -- --
-- RTSMD -- UTXBRK -- -- -- -- -- -- RTSMD -- UTXBRK -- -- -- -- --
-- -- -- UTXEN -- -- -- -- -- -- -- -- UTXEN -- -- -- -- --
-- -- UTXBF -- -- -- -- -- -- -- UTXBF -- -- -- -- --
-- ADM_EN TRMT -- TX8 -- RX8 -- -- ADM_EN TRMT -- TX8 -- RX8 --
-- WAKE
-- LPBACK
-- ABAUD ADDEN -- -- --
-- RXINV RIDLE -- -- --
-- BRGH PERR -- -- --
--
--
-- STSEL
UEN<1:0>
PDSEL<1:0>
ADDR<7:0> URXISEL<1:0> -- -- -- -- WAKE -- -- --
UTXISEL<1:0>
Transmit Register Receive Register
BRG<15:0> UEN<1:0> PDSEL<1:0>
6200 U2MODE(1) 6210 6220 6230 6240 U2STA
(1)
ADDR<7:0> URXISEL<1:0> -- -- -- -- -- --
UTXISEL<1:0>
U2TXREG U2RXREG U2BRG(1)
Transmit Register Receive Register
Legend: Note 1:
15:0 BRG<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-12:
Virtual Address (BF80_#) Bit Range Register Name
SPI1-2 REGISTERS MAP(1,2)
Bits All Resets
0000 0000 0000 0008 0000 0000 -- -- FRMEN ON -- -- -- -- -- -- -- -- -- SIDL -- -- -- -- -- DISSDO -- -- -- -- -- MODE32 -- SPIBUSY -- -- -- MODE16 -- -- -- -- -- SMP -- -- -- CKE -- -- -- SSEN -- -- -- CKP -- SPIROV -- MSTEN -- -- -- -- -- -- -- BRG<8:0> -- -- -- -- -- -- -- SPITBE -- -- -- -- SPIFE -- -- -- -- -- -- SPIRBF -- -- -- -- 0000 0000 0008 0000 0000 0008 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 61
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5800
SPI1CON
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
FRMEN ON -- --
FRMSYNC FRMPOL -- -- -- SIDL -- --
-- DISSDO -- --
-- MODE32 -- SPIBUSY
-- MODE16 -- --
-- SMP -- --
-- CKE -- --
-- SSEN -- --
-- CKP -- SPIROV
-- MSTEN -- --
-- -- -- --
-- -- -- SPITBE
-- -- -- --
SPIFE -- -- --
-- -- -- SPIRBF
5810 SPI1STAT 5820 5830 SPI1BUF SPI1BRG
DATA<31:0>
5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF
FRMSYNC FRMPOL
DATA<31:0>
5A30 SPI2BRG Legend: Note 1: 2:
15:0 -- -- -- -- -- -- -- BRG<8:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices.
PIC32MX3XX/4XX
DS61143H-page 62 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-13:
Virtual Address (BF80_#) Bit Range Register Name
ADC REGISTERS MAP
Bits All Resets
0000 0000 0000 0000 0000 0000 CH0SA<3:0> -- -- PCFG3 -- CSSL3 -- -- PCFG2 -- CSSL2 -- -- PCFG1 -- CSSL1 -- -- PCFG0 -- CSSL0 0000 0000 0000 0000 0000 0000 0000 0000 ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 9100 ADC1BUF9 Legend: Note 1:
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON -- VCFG2 -- ADRC CH0NB -- -- PCFG15 -- CSSL15
-- -- -- VCFG1 -- -- -- -- -- PCFG14 -- CSSL14
-- SIDL -- VCFG0 -- -- -- -- -- PCFG13 -- CSSL13
-- -- -- OFFCAL -- -- -- -- PCFG12 -- CSSL12
-- -- -- -- --
-- -- CSCNA -- SAMC<4:0>
-- FORM<2:0> -- -- --
-- -- -- --
-- -- BUFS -- CH0NA
-- SSRC<2:0> -- -- -- -- -- -- PCFG6 -- CSSL6
-- -- -- -- -- -- PCFG5 -- CSSL5
-- CLRASAM -- -- -- -- -- PCFG4 -- CSSL4
-- -- -- --
-- ASAM -- --
-- SAMP -- BUFM --
-- DONE -- ALTS --
SMPI<3:0> ADCS<7:0>
CH0SB<3:0> -- -- PCFG11 -- CSSL11 -- -- PCFG10 -- CSSL10 -- -- PCFG9 -- CSSL9 -- -- PCFG8 -- CSSL8
-- -- PCFG7 -- CSSL7
ADC Result Word 0 (ADC1BUF0<31:0>)
ADC Result Word 9 (ADC1BUF9<31:0>) 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-13:
Virtual Address (BF80_#) Bit Range Register Name
ADC REGISTERS MAP (CONTINUED)
Bits All Resets
0000 0000 ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 63
31/15
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27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9110 ADC1BUFA 9120 ADC1BUFB 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF Legend: Note 1:
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
ADC Result Word A (ADC1BUFA<31:0>)
ADC Result Word F (ADC1BUFF<31:0>) 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
PIC32MX3XX/4XX
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR Legend: Note 1:
31:16 15:0 31:16 15:0 31:16
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
-- -- --
-- CRCEN -- --
-- CRCAPP -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- --
-- -- --
0000 0000 0000 0000 0000
PLEN<3:0>
CRCCH<1:0>
DCRCDATA<15:0>
15:0 DCRCXOR<15:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61143H-page 64 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-14:
Virtual Address (BF88_#) Bit Range Register Name
DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
Bits All Resets
0000 0000 0000 0000 0000 0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3000 DMACON(1) 3010 DMASTAT
31:16 15:0 31:16 15:0 31:16
-- ON -- --
-- -- -- --
-- SIDL -- --
-- SUSPEND -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- RDWR
-- -- -- --
-- -- --
-- -- --
DMACH<1:0>
3020 DMAADDR Legend: Note 1:
DMAADDR<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-15:
DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1)
Bits
(c) 2011 Microchip Technology Inc. DS61143H-page 65
TABLE 4-16:
Virtual Address (BF88_#)
DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1)
Bits All Resets
0000 0000 00FF -- CHCCIE CHCCIF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000 CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CFORCE -- -- CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF -- CHEN -- CHAED -- CHCHN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3060 DCH0CON 3070 DCH0ECON 3080 3090 DCH0INT DCH0SSA
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- CHCHNS --
-- CHEN CFORCE
-- CHAED CABORT CHSHIE CHSHIF
-- CHCHN PATEN CHDDIE CHDDIF
-- CHAEN SIRQEN CHDHIE CHDHIF
-- -- AIRQEN CHBCIE CHBCIF
-- CHEDET
--
--
CHPRI<1:0>
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
CHSSA<31:0>
30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT
CHSSIZ<7:0> CHDSIZ<7:0> CHSTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0>
PIC32MX3XX/4XX
3120 DCH1CON 3130 DCH1ECON 3140 3150 DCH1INT DCH1SSA
CHAIRQ<7:0>
CHSIRQ<7:0>
Legend: Note 1:
0000 CHSSA<31:0> 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-16:
Virtual Address (BF88_#)
DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) (CONTINUED)
Bits All Resets Bit Range
DS61143H-page 66 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3160
DCH1DSA
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHCHNS -- CFORCE -- -- CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF -- CHEN -- CHAED -- CHCHN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF -- -- -- -- -- -- -- -- -- AIRQEN CHBCIE CHBCIF -- -- -- -- -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000
3170 DCH1SSIZ 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 3210 3220 DCH2INT DCH2SSA DCH2DSA
CHSSIZ<7:0> CHDSIZ<7:0> CHSPTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0>
CHAIRQ<7:0>
CHSIRQ<7:0>
CHSSA<31:0> CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
0000 0000 0000 0000 0000 0000 0000
3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR Legend: Note 1:
CHSSIZ<7:0> CHDSIZ<7:0>
-- -- -- -- -- -- -- -- CHSPTR<7:0> 0000 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-16:
Virtual Address (BF88_#)
DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY(1) (CONTINUED)
Bits All Resets
0000 0000 -- -- -- -- CHEDET -- CHCCIE CHCCIF -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 00FF -- CHTAIE CHTAIF -- CHERIE CHERIF FF00 0000 0000 0000 0000 CHDSA<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 67
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
3260 DCH2DPTR 3270 DCH2CSIZ 3280 DCH2CPTR 3290 DCH2DAT
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- CHCHNS --
-- -- -- -- -- CHEN CFORCE
-- -- -- -- -- CHAED CABORT CHSHIE CHSHIF
-- -- -- -- -- CHCHN PATEN CHDDIE CHDDIF
-- -- -- -- -- CHAEN SIRQEN CHDHIE CHDHIF
-- -- -- -- -- -- AIRQEN CHBCIE CHBCIF
--
--
--
CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0> CHPDAT<7:0> CHPRI<1:0>
32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT
CHAIRQ<7:0> CHSDIE CHSDIF
CHSIRQ<7:0> -- --
32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT
CHSSA<31:0>
PIC32MX3XX/4XX
CHSSIZ<7:0> CHDSIZ<7:0> CHSTR<7:0> CHDPTR<7:0> CHCSIZ<7:0> CHCPTR<7:0>
Legend: Note 1:
15:0 -- -- -- -- -- -- -- -- CHPDAT<7:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-17:
Virtual Address (BF80_#) Bit Range Register Name
COMPARATOR REGISTERS MAP(1)
Bits All Resets
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
9800
CVRCON
31:16
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0000
Legend: Note 1:
15:0 ON -- -- -- -- -- -- -- -- CVROE CVRR CVRSS CVR<3:0> 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61143H-page 68 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
A000 A010 A060
CM1CON CM2CON CMSTAT
31:16 15:0 31:16 15:0 31:16
-- ON -- ON --
-- COE -- COE --
-- CPOL -- CPOL --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- COUT -- COUT --
-- -- --
-- -- --
-- -- -- -- --
-- CREF -- CREF --
-- -- -- -- --
-- -- -- -- --
-- -- --
-- -- --
0000 00C3 0000 00C3 0000
EVPOL<1:0> EVPOL<1:0>
CCH<1:0> CCH<1:0>
Legend: Note 1:
15:0 -- -- SIDL -- -- -- -- -- -- -- -- -- -- -- C2OUT C1OUT 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-18:
COMPARATOR VOLTAGE REFERENCE REGISTERS MAP(1)
Bits
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register Name
(c) 2011 Microchip Technology Inc. DS61143H-page 69
TABLE 4-19:
Virtual Address (BF80_#) Bit Range Register Name
FLASH CONTROLLER REGISTERS MAP
Bits All Resets
0000 0000 0000 0000 NVMADDR<31:0> NVMDATA<31:0> 0000 0000 0000 0000 0000 0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F400 NVMCON(1) F410 NVMKEY
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- WR
-- WREN
-- WRERR
-- LVDERR
-- LVDSTAT
-- --
-- --
-- --
-- --
-- --
-- --
-- --
--
--
--
--
NVMOP<3:0>
NVMKEY<31:0>
F420 NVMADDR(1) F430 F440 NVMDATA NVMSRC ADDR
Legend: Note 1:
NVMSRCADDR<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-20:
SYSTEM CONTROL REGISTERS MAP(1,2)
Bits
PIC32MX3XX/4XX
F000 OSCCON
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- ON -- -- -- --
--
PLLODIV<2:0> COSC<2:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
FRCDIV<2:0> NOSC<2:0> -- -- -- -- -- CMR -- -- -- -- -- -- -- VREGS -- --
-- CLKLOCK -- -- -- -- -- EXTR -- --
SOSCRDY ULOCK -- -- -- -- SWR -- --
-- SLOCK -- -- -- -- -- --
PBDIV<1:0> SLPEN -- -- SWDTPS<4:0> -- WDTO -- -- -- SLEEP -- -- -- IDLE -- -- CF -- --
PLLMULT<2:0> UFRCEN -- -- SOSCEN -- -- -- -- BOR -- -- OSWEN -- -- -- POR -- SWRST
0000 0000 0000 0000 0000
F010 OSCTUN
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
TUN<5:0>
0000 WDTCON F600 RCON
WDTCLR 0000 0000 0000 0000 0000 0000
F610 RSWRST F230 SYSKEY(3) Legend: Note 1: 2: 3:
SYSKEY<31:0> 15:0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. This register does not have associated CLR, SET, and INV registers.
Virtual Address (BF88_#)
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6040 6050 6060
TRISB PORTB LATB ODCB
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- TRISB15 -- RB15 -- LATB15 --
-- TRISB14 -- RB14 -- LATB14 --
-- TRISB13 -- RB13 -- LATB13 --
-- TRISB12 -- RB12 -- LATB12 --
-- TRISB11 -- RB11 -- LATB11 --
-- TRISB10 -- RB10 -- LATB10 --
-- TRISB9 -- RB9 -- LATB9 --
-- TRISB8 -- RB8 -- LATB8 --
-- TRISB7 -- RB7 -- LATB7 --
-- TRISB6 -- RB6 -- LATB6 --
-- TRISB5 -- RB5 -- LATB5 --
-- TRISB4 -- RB4 -- LATB4 --
-- TRISB3 -- RB3 -- LATB3 --
-- TRISB2 -- RB2 -- LATB2 --
-- TRISB1 -- RB1 -- LATB1 --
-- TRISB0 -- RB0 -- LATB0 --
0000 FFFF 0000 xxxx 0000 xxxx 0000
6070 Legend: Note 1:
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61143H-page 70 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-21:
PORTA REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 C6FF 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6000 6010 6020 6030 Legend: Note 1:
TRISA PORTA LATA ODCA
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- TRISA15 -- RA15 -- LATA15 --
-- TRISA14 -- RA14 -- LATA14 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISA10 -- RA10 -- LATA10 --
-- TRISA9 -- RA9 -- LATA9 --
-- -- -- -- -- -- --
-- TRISA7 -- RA7 -- LATA7 --
-- TRISA6 -- RA6 -- LATA6 --
-- TRISA5 -- RA5 -- LATA5 --
-- TRISA4 -- RA4 -- LATA4 --
-- TRISA3 -- RA3 -- LATA3 --
-- TRISA2 -- RA2 -- LATA2 --
-- TRISA1 -- RA1 -- LATA1 --
-- TRISA0 -- RA0 -- LATA0 --
15:0 ODCA15 ODCA14 -- -- -- ODCA10 ODCA9 -- ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-22:
PORTB REGISTERS MAP(1)
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register Name
(c) 2011 Microchip Technology Inc. DS61143H-page 71
TABLE 4-23:
Virtual Address (BF88_#)
PORTC REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 F01E 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6080 6090 60A0 60B0 Legend: Note 1:
TRISC PORTC LATC ODCC
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- TRISC15 -- RC15 -- LATC15 --
-- TRISC14 -- RC14 -- LATC14 --
-- TRISC13 -- RC13 -- LATC13 --
-- TRISC12 -- RC12 -- LATC12 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISC4 -- RC4 -- LATC4 --
-- TRISC3 -- RC3 -- LATC3 --
-- TRISC2 -- RC2 -- LATC2 --
-- TRISC1 -- RC1 -- LATC1 --
-- -- -- -- -- -- --
15:0 ODCC15 ODCC14 ODCC13 ODCC12 -- -- -- -- -- -- -- ODCC4 ODCC3 ODCC2 ODCC1 -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-24:
PORTC REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1)
Bits
PIC32MX3XX/4XX
6080 6090 60A0 60B0 Legend: Note 1:
TRISC PORTC LATC ODCC
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- TRISC15 -- RC15 -- LATC15 --
-- TRISC14 -- RC14 -- LATC14 --
-- TRISC13 -- RC13 -- LATC13 --
-- TRISC12 -- RC12 -- LATC12 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
0000 F000 0000 xxxx 0000 xxxx 0000
15:0 ODCC15 ODCC14 ODCC13 ODCC12 -- -- -- -- -- -- -- -- -- -- -- -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
60C0 60D0
TRISD PORTD LATD ODCD
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISD11 -- RD11 -- LATD11 --
-- TRISD10 -- RD10 -- LATD10 --
-- TRISD9 -- RD9 -- LATD9 --
-- TRISD8 -- RD8 -- LATD8 --
-- TRISD7 -- RD7 -- LATD7 --
-- TRISD6 -- RD6 -- LATD6 --
-- TRISD5 -- RD5 -- LATD5 --
-- TRISD4 -- RD4 -- LATD4 --
-- TRISD3 -- RD3 -- LATD3 --
-- TRISD2 -- RD2 -- LATD2 --
-- TRISD1 -- RD1 -- LATD1 --
-- TRISD0 -- RD0 -- LATD0 --
0000 0FFF 0000 xxxx 0000 xxxx 0000
60E0 60F0 Legend: Note 1:
15:0 -- -- -- -- ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61143H-page 72 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-25:
PORTD REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 FFFF 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
60C0 60D0 60E0 60F0 Legend: Note 1:
TRISD PORTD LATD ODCD
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- TRISD15 -- RD15 -- LATD15 --
-- TRISD14 -- RD14 -- LATD14 --
-- TRISD13 -- RD13 -- LATD13 --
-- TRISD12 -- RD12 -- LATD12 --
-- TRISD11 -- RD11 -- LATD11 --
-- TRISD10 -- RD10 -- LATD10 --
-- TRISD9 -- RD9 -- LATD9 --
-- TRISD8 -- RD8 -- LATD8 --
-- TRISD7 -- RD7 -- LATD7 --
-- TRISD6 -- RD6 -- LATD6 --
-- TRISD5 -- RD5 -- LATD5 --
-- TRISD4 -- RD4 -- LATD4 --
-- TRISD3 -- RD3 -- LATD3 --
-- TRISD2 -- RD2 -- LATD2 --
-- TRISD1 -- RD1 -- LATD1 --
-- TRISD0 -- RD0 -- LATD0 --
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-26:
PORTD REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1)
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register Name
(c) 2011 Microchip Technology Inc. DS61143H-page 73
TABLE 4-27:
Virtual Address (BF88_#)
PORTE REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 03FF 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6100 6110 6120 6130 Legend: Note 1:
TRISE PORTE LATE ODCE
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISE9 -- RE9 -- LATE9 --
-- TRISE8 -- RE8 -- LATE8 --
-- TRISE7 -- RE7 -- LATE7 --
-- TRISE6 -- RE6 -- LATE6 --
-- TRISE5 -- RE5 -- LATE5 --
-- TRISE4 -- RE4 -- LATE4 --
-- TRISE3 -- RE3 -- LATE3 --
-- TRISE2 -- RE2 -- LATE2 --
-- TRISE1 -- RE1 -- LATE1 --
-- TRISE0 -- RE0 -- LATE0 --
15:0 -- -- -- -- -- -- ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-28:
PORTE REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1)
Bits
PIC32MX3XX/4XX
6100 6110 6120 6130 Legend: Note 1:
TRISE PORTE LATE ODCE
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISE7 -- RE7 -- LATE7 --
-- TRISE6 -- RE6 -- LATE6 --
-- TRISE5 -- RE5 -- LATE5 --
-- TRISE4 -- RE4 -- LATE4 --
-- TRISE3 -- RE3 -- LATE3 --
-- TRISE2 -- RE2 -- LATE2 --
-- TRISE1 -- RE1 -- LATE1 --
-- TRISE0 -- RE0 -- LATE0 --
0000 00FF 0000 xxxx 0000 xxxx 0000
15:0 -- -- -- -- -- -- -- -- ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6140 6150 6160
TRISF PORTF LATF ODCF
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF13 -- RF13 -- LATF13 --
-- TRISF12 -- RF12 -- LATF12 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF8 -- RF8 -- LATF8 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF5 -- RF5 -- LATF5 --
-- TRISF4 -- RF4 -- LATF4 --
-- TRISF3 -- RF3 -- LATF3 --
-- TRISF2 -- RF2 -- LATF2 --
-- TRISF1 -- RF1 -- LATF1 --
-- TRISF0 -- RF0 -- LATF0 --
0000 313F 0000 xxxx 0000 xxxx 0000
6170 Legend: Note 1:
15:0 -- -- ODCF13 ODCF12 -- -- -- ODCF8 -- -- ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61143H-page 74 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-29:
PORTF REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L AND PIC32MX360F512L DEVICES ONLY(1)
Bits All Resets
0000 31FF 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6140 6150 6160 6170
TRISF PORTF LATF ODCF
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF13 -- RF13 -- LATF13 --
-- TRISF12 -- RF12 -- LATF12 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF8 -- RF8 -- LATF8 --
-- TRISF7 -- RF7 -- LATF7 --
-- TRISF6 -- RF6 -- LATF6 --
-- TRISF5 -- RF5 -- LATF5 --
-- TRISF4 -- RF4 -- LATF4 --
-- TRISF3 -- RF3 -- LATF3 --
-- TRISF2 -- RF2 -- LATF2 --
-- TRISF1 -- RF1 -- LATF1 --
-- TRISF0 -- RF0 -- LATF0 --
Legend: Note 1:
15:0 -- -- ODCF13 ODCF12 -- -- -- ODCF8 ODCF7 ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-30:
PORTF REGISTERS MAP FOR PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6140 6150 6160 6170
TRISF PORTF LATF ODCF
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF5 -- RF5 -- LATF5 --
-- TRISF4 -- RF4 -- LATF4 --
-- TRISF3 -- RF3 -- LATF3 --
-- TRISF2 -- RF2 -- LATF2 --
-- TRISF1 -- RF1 -- LATF1 --
-- TRISF0 -- RF0 -- LATF0 --
All Resets
Bit Range
Register Name
(c) 2011 Microchip Technology Inc. DS61143H-page 75
TABLE 4-31:
Virtual Address (BF88_#)
PORTF REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H AND PIC32MX340F512H DEVICES ONLY(1)
Bits All Resets
0000 07FF 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6140 6150 6160 6170
TRISF PORTF LATF ODCF
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISF6 -- RF6 -- LATF6 --
-- TRISF5 -- RF5 -- LATF5 --
-- TRISF4 -- RF4 -- LATF4 --
-- TRISF3 -- RF3 -- LATF3 --
-- TRISF2 -- RF2 -- LATF2 --
-- TRISF1 -- RF1 -- LATF1 --
-- TRISF0 -- RF0 -- LATF0 --
Legend: Note 1:
15:0 -- -- -- -- -- -- -- -- -- ODCF6 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-32:
PORTF REGISTERS MAP FOR PIC32MX420F032H, PIC32MX440F128H AND PIC2MX440F256H DEVICES ONLY(1)
Bits
PIC32MX3XX/4XX
0000 03FF 0000 xxxx 0000 xxxx 0000
Legend: Note 1:
15:0 -- -- -- -- -- -- -- -- -- -- ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF88_#)
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6180 6190
TRISG PORTG LATG ODCG
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISG9 -- RG9 -- LATG9 --
-- TRISG8 -- RG8 -- LATG8 --
-- TRISG7 -- RG7 -- LATG7 --
-- TRISG6 -- RG6 -- LATG6 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISG3 -- RG3 -- LATG3 --
-- TRISG2 -- RG2 -- LATG2 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
0000 03cc 0000 xxxx 0000 xxxx 0000
61A0 61B0 Legend: Note 1:
15:0 -- -- -- -- -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 -- -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
All Resets
Bit Range
Register Name
DS61143H-page 76 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-33:
PORTG REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 F3CF 0000 xxxx 0000 xxxx 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
6180 6190 61A0 61B0 Legend: Note 1:
TRISG PORTG LATG ODCG
31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- TRISG15 -- RG15 -- LATG15 --
-- TRISG14 -- RG14 -- LATG14 --
-- TRISG13 -- RG13 -- LATG13 --
-- TRISG12 -- RG12 -- LATG12 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISG9 -- RG9 -- LATG9 --
-- TRISG8 -- RG8 -- LATG8 --
-- TRISG7 -- RG7 -- LATG7 --
-- TRISG6 -- RG6 -- LATG6 --
-- -- -- -- -- -- --
-- -- -- -- -- -- --
-- TRISG3 -- RG3 -- LATG3 --
-- TRISG2 -- RG2 -- LATG2 --
-- TRISG1 -- RG1 -- LATG1 --
-- TRISG0 -- RG0 -- LATG0 --
15:0 ODCG15 ODCG14 ODCG13 ODCG12 -- -- ODCG9 ODCG8 ODCG7 ODCG6 -- -- ODCG3 ODCG2 ODCG1 ODCG0 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-34:
PORTG REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1)
Bits
Virtual Address (BF88_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register Name
(c) 2011 Microchip Technology Inc. DS61143H-page 77
TABLE 4-35:
Virtual Address (BF88_#)
CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY(1)
Bits All Resets
0000 0000 0000 0000
Bit Range
Register Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
61C0 61D0 61E0
CNCON CNEN CNPUE
31:16 15:0 31:16 15:0 31:16
-- ON -- CNEN15 --
-- -- -- CNEN14 --
-- SIDL -- CNEN13 --
-- -- -- CNEN12 --
-- -- -- CNEN11 --
-- -- -- CNEN10 --
-- -- -- CNEN9 --
-- -- -- CNEN8 --
-- -- -- CNEN7 --
-- -- -- CNEN6 --
-- -- CNEN21 CNEN5 CNPUE21
-- -- CNEN20 CNEN4 CNPUE20
-- -- CNEN19 CNEN3
-- -- CNEN18 CNEN2
-- -- CNEN17 CNEN1
-- -- CNEN16 CNEN0
CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
Legend: Note 1:
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-36:
CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H DEVICES ONLY(1)
Bits
PIC32MX3XX/4XX
61C0 61D0 61E0
CNCON CNEN CNPUE
31:16 15:0 31:16 15:0 31:16
-- ON -- CNEN15 --
-- -- -- CNEN14 --
-- SIDL -- CNEN13 --
-- -- -- CNEN12 --
-- -- -- CNEN11 --
-- -- -- CNEN10 --
-- -- -- CNEN9 --
-- -- -- CNEN8 --
-- -- -- CNEN7 --
-- -- -- CNEN6 --
-- -- -- CNEN5 --
-- -- -- CNEN4 --
-- -- -- CNEN3 --
-- -- CNEN18 CNEN2
-- -- CNEN17 CNEN1
-- -- CNEN16 CNEN0
0000 0000 0000 0000
CNPUE18 CNPUE17 CNPUE16 0000
Legend: Note 1:
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE1 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
Virtual Address (BF80_#)
Virtual Address (BF80_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F200 Legend:
DDPCON
31:16
--
--
--
--
--
--
--
--
-- --
-- --
-- --
-- --
-- JTAGEN
-- TROEN
-- --
-- --
0000 0008
15:0 -- -- -- -- -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
All Resets
Bit Range
Register Name
DS61143H-page 78 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
TABLE 4-37:
Bit Range Register Name
PARALLEL MASTER PORT REGISTERS MAP(1)
Bits All Resets
0000 0000 0000 0000 0000 0000 0000 0000 DATAIN<31:0> -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000 0000 0000 0000 0000
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
7000
PMCON
31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON -- BUSY --
-- -- -- --
-- SIDL -- --
-- -- --
-- -- --
-- PMPTTL -- MODE16 --
-- PTWREN -- --
-- PTRDEN -- --
-- -- --
-- -- --
-- ALP -- --
-- CS2P -- --
-- CS1P -- --
-- -- -- --
-- WRSP -- --
-- RDSP -- --
ADRMUX<1:0> INCM<1:0>
CSF<1:0> WAITB<1:0> ADDR<13:0>
7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7050 7060 PMDIN PMAEN PMSTAT
IRQM<1:0>
MODE<1:0>
WAITM<3:0>
WAITE<1:0>
15:0 CS2EN/A15 CS1EN/A14
DATAOUT<31:0>
PTEN<15:0>
Legend: Note 1:
15:0 IBF IBOV -- -- IB3F IB2F IB1F IB0F OBE OBUF -- -- OB3E OB2E OB1E OB0E 008F x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-38:
PROGRAMMING AND DIAGNOSTICS REGISTERS MAP
Bits
TABLE 4-39:
Virtual Address (BF88_#) Register Name
PREFETCH REGISTERS MAP
Bits All Resets
0000 00xx -- -- -- xxx0 xxx2 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx CHELRU<24:16> CHELRU<15:0> CHEHIT<31:0> CHEMIS<31:0> 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx
(c) 2011 Microchip Technology Inc. DS61143H-page 79
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
4000 CHECON(1) 4010 CHEACC(1) 4020 CHETAG
(1)
31:16 15:0 15:0
-- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- --
-- -- -- -- -- -- LMASK<15:5>
-- -- DCSZ<1:0> -- -- -- -- -- -- -- --
-- -- -- --
-- -- -- --
-- -- PREFEN<1:0> -- -- -- --
-- -- --
--
-- CHECOH 0000 PFMWS<2:0> 0007 --
31:16 CHEWEN -- 31:16 LTAGBOOT 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 -- --
-- -- CHEIDX<3:0> LLOCK -- -- LTYPE -- --
LTAG<23:16> LVALID -- -- -- -- -- -- --
LTAG<15:4>
4030 CHEMSK(1) 4040 4050 4060 4070 4080 4090 40A0 CHEW0 CHEW1 CHEW2 CHEW3 CHELRU CHEHIT CHEMIS
CHEW0<31:0> CHEW1<31:0> CHEW2<31:0> CHEW3<31:0> -- -- -- -- -- --
PIC32MX3XX/4XX
40C0 CHEPFABT Legend: Note 1:
CHEPFABT<31:0> 15:0 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-40:
Virtual Address (BF80_#) Bit Range Register Name
RTCC REGISTERS MAP(1)
Bits All Resets
Virtual Address (BFC0_#)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
2FF0 2FF4 2FF8
DEVCFG3 DEVCFG2 DEVCFG1
31:16 31:16 15:0 31:16 15:0 31:16
-- -- UPLLEN(1) -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- CP
-- -- -- -- -- --
-- -- -- OSCIOFNC --
-- -- UPLLIDIV<2:0>(1) -- --
-- USERID8 -- -- BWP
-- USERID7 -- -- FWDTEN IESO -- --
-- USERID6 -- -- -- -- --
-- USERID5 -- FPLLMUL<2:0> -- FSOSCEN -- --
-- USERID4 --
-- USERID3 -- --
-- USERID2
-- USERID1 FPLLODIV<2:0> FPLLIDIV<2:0>
--
xxxx
15:0 USERID15 USERID14 USERID13 USERID12 USERID11 USERID10 USERID9
USERID0 xxxx xxxx xxxx xxxx xxxx PWP16 xxxx xxxx
WDTPS<4:0> -- -- -- -- PWP19 ICESEL PWP18 -- FNOSC<2:0> PWP17 DEBUG<1:0>
FCKSM<1:0>
FPBDIV<1:0>
POSCMOD<1:0>
2FFC DEVCFG0 Legend: Note 1:
15:0 PWP15 PWP14 PWP13 PWP12 -- -- -- -- x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. These bits are only available on PIC32MX4XX devices.
All Resets
Bit Range
Register Name
DS61143H-page 80 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0200 0210 0220 0230
RTCCON RTCALRM RTCTIME RTCDATE
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- ON -- ALRMEN
-- -- -- CHIME
-- SIDL -- PIV
-- -- -- ALRMSYNC
-- -- --
-- -- -- -- -- -- -- RTSECSEL RTCCLKON -- --
CAL<11:0> -- -- -- -- RTCWREN RTCSYNC HALFSEC -- -- -- RTCOE --
0000 0000 0000 0000 MIN01<3:0> xxxx -- xx00 xxxx xx0x xxxx -- xx00 00xx
AMASK<3:0> HR01<3:0> SEC01<3:0> YEAR01<3:0> DAY01<3:0> MIN01<3:0> SEC01<3:0> -- -- -- -- MIN10<3:0> -- -- -- -- -- --
ARPT<7:0> -- -- -- -- -- -- --
HR10<3:0> SEC10<3:0> YEAR10<3:0> DAY10<3:0> MIN10<3:0> SEC10<3:0> -- -- -- -- --
MONTH10<3:0> MIN10<3:0> MONTH10<3:0>
MONTH01<3:0> WDAY01<3:0> MIN01<3:0> -- -- MONTH01<3:0>
0240 ALRMTIME 0250 ALRMDATE Legend: Note 1:
--
--
15:0 DAY10<3:0> DAY01<3:0> -- -- -- -- WDAY01<3:0> xx0x x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information.
TABLE 4-41:
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Bits
TABLE 4-42:
Virtual Address (BF80_#) Register Name
DEVICE AND REVISION ID SUMMARY
Bits All Resets
xxxx xxxx
(c) 2011 Microchip Technology Inc. DS61143H-page 81
Bit Range
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F220 Legend:
DEVID
31:16
VER<3:0>
DEVID<27:16>
15:0 DEVID<15:0> x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal.
PIC32MX3XX/4XX
TABLE 4-43:
Virtual Address (BF88_#) Bit Range Register Name
USB REGISTERS MAP(1)
Bits All Resets
DS61143H-page 82 (c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5040 5050 5060 5070 5080
U1OTG IR(2) U1OTG IE U1OTG STAT(3) U1OTG CON U1PWRC
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- IDIF -- IDIE -- ID -- -- UACTPND(4) -- STALLIF -- STALLIE -- BTSEF -- BTSEE -- -- JSTATE(4) -- LSPDEN --
-- -- -- -- -- -- -- --
-- -- -- LSTATE -- -- -- --
-- ACTVIF -- ACTVIE -- -- -- -- USLPGRD -- IDLEIF -- IDLEIE -- BTOEF -- BTOEE -- -- USBRST -- --
-- -- -- SESVD -- -- -- -- TRNIF -- TRNIE -- DFN8EF -- DFN8EE -- DIR -- HOSTEN -- DEVADDR<6:0> --
-- -- -- SESEND -- OTGEN -- -- -- SOFIF -- SOFIE -- CRC16EF -- CRC16EE -- PPBI -- RESUME -- --
-- -- -- -- -- -- -- -- -- UERRIF -- UERRIE -- CRC5EF EOFEF -- CRC5EE EOFEE -- -- -- PPBRST -- --
-- VBUSVDIF 0000 -- -- -- -- -- URSTIF -- URSTIE -- PIDEF -- PIDEE -- -- -- USBEN SOFEN -- -- 0000 VBUSVDIE 0000 0000 VBUSVD 0000 0000
T1MSECIF LSTATEIF T1MSECIE LSTATEIE
SESVDIF SESENDIF SESVDIE SESENDIE
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
VBUSCHG VBUSDIS 0000 0000 USUSPEND USBPWR 0000 0000 0000
5200
U1IR(2)
15:0 31:16
ATTACHIF RESUMEIF -- --
DETACHIF 0000 0000 0000
5210
U1IE
15:0 31:16
ATTACHIE RESUMEIE -- BMXEF -- BMXEE -- -- SE0(4) -- -- -- DMAEF -- DMAEE -- -- PKTDIS TOKBUSY -- --
DETACHIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
5220
U1EIR
15:0 31:16
5230
U1EIE
15:0 31:16 15:0 31:16
5240 U1STAT(3)
ENDPT<3:0>(4)
5250
U1CON
15:0 31:16 15:0 31:16
5260
U1ADDR
5270 U1BDTP1 Legend: Note 1: 2: 3: 4:
15:0 -- -- -- -- -- -- -- -- BDTPTRL<7:1> -- 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers. All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported. The reset value for this bit is undefined.
TABLE 4-43:
Virtual Address (BF88_#) Bit Range Register Name
USB REGISTERS MAP(1) (CONTINUED)
Bits All Resets
0000 0000 -- -- -- -- -- -- -- -- -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- -- EP<3:0> -- -- -- -- USBFRZ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CNT<7:0> -- -- -- UTEYE -- LSPD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- UOEMON -- RETRYDIS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- USBSIDL -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- -- -- -- -- -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- -- -- -- -- -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- -- -- -- -- -- -- -- -- -- -- -- -- BDTPTRH<7:0> BDTPTRU<7:0> -- -- -- -- -- FRMH<10:8> -- -- -- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
(c) 2011 Microchip Technology Inc. DS61143H-page 83
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5280 U1FRML(3) 5290 U1FRMH(3) 52A0 52B0 U1TOK U1SOF
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- --
-- -- -- -- PID<3:0> --
-- -- -- --
-- FRML<7:0> -- -- --
--
--
--
--
52C0 U1BDTP2 52D0 U1BDTP3 52E0 U1CNFG1 5300 5310 5320 5330 5340 5350 5360 5370 Legend: Note 1: 2: 3: 4: U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 U1EP7
EPHSHK 0000 EPHSHK 0000 EPHSHK 0000
PIC32MX3XX/4XX
0000
EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000
15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers. All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported. The reset value for this bit is undefined.
TABLE 4-43:
Virtual Address (BF88_#) Bit Range Register Name
USB REGISTERS MAP(1) (CONTINUED)
Bits All Resets
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PIC32MX3XX/4XX
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5380 5390 53A0 53B0 53C0 53D0 53E0 53F0
U1EP8 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 U1EP14 U1EP15
31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS -- EPCONDIS --
-- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN -- EPRXEN --
-- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN -- EPTXEN --
-- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL -- EPSTALL --
-- -- -- -- -- -- -- --
0000
EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000 EPHSHK 0000 0000
Legend: Note 1: 2: 3: 4:
15:0 -- -- -- -- -- -- -- -- -- -- -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 x = unknown value on Reset, -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 "CLR, SET and INV Registers" for more information. This register does not have associated CLR, SET, and INV registers. All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported. The reset value for this bit is undefined.
PIC32MX3XX/4XX
5.0 FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. "Flash Program Memory" (DS61121) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX3XX/4XX devices contain an internal program Flash memory for executing user code. There are three methods by which the user can program this memory: * Run-Time Self Programming (RTSP) * In-Circuit Serial ProgrammingTM (ICSPTM) * EJTAG Programming RTSP is performed by software executing from either Flash or RAM memory. EJTAG is performed using the EJTAG port of the device and a EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. RTSP techniques are described in this chapter. The ICSP and EJTAG methods are described in the "PIC32MX Flash Programming Specification" (DS61145), which can be downloaded from the Microchip web site. Note: Flash LVD Delay (LVDstartup) must be taken into account between setting up and executing any Flash command operation. See Example 5-1 for a code example to set up and execute a Flash command operation.
EXAMPLE 5-1:
NVMCON = 0x4004; Wait(delay); NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; NVMCONSET = 0x8000; while(NVMCONbits.WR==1); // Enable and configure for erase operation // Delay for 6 s for LVDstartup
// Initiate operation // Wait for current operation to complete
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NOTES:
DS61143H-page 86
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PIC32MX3XX/4XX
6.0 RESETS
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. "Resets" (DS61118) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: * * * * * * POR: Power-on Reset MCLR: Master Clear Reset Pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset
A simplified block diagram of the Reset module is illustrated in Figure 6-1.
FIGURE 6-1:
MCLR
SYSTEM RESET BLOCK DIAGRAM
Glitch Filter
MCLR
Sleep or Idle Voltage Regulator Enabled WDT Time-out
WDTR
Power-up Timer VDD VDD Rise Detect Brown-out Reset
POR SYSRST
BOR
Configuration Mismatch Reset Software Reset
CMR SWR
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NOTES:
DS61143H-page 88
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PIC32MX3XX/4XX
7.0 INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. "Interrupt Controller" (DS61108) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. PIC32MX3XX/4XX devices generate interrupt requests in response to interrupt events from peripheral modules. The Interrupt Control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. The PIC32MX3XX/4XX interrupts module includes the following features: * * * * * * * * * * * * Up to 96 interrupt sources Up to 64 interrupt vectors Single and Multi-Vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Module Freeze in Debug mode Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Dedicated shadow set for highest priority level Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE
Interrupt Requests
Vector Number
Interrupt Controller Priority Level
CPU Core
Shadow Set Number
Note:
Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them are available in Section 3.0 "CPU". To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only. The CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register.
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TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION
IRQ Vector Number Flag 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 23 24 24 24 25 25 25 26 27 28 29 30 IFS0<0> IFS0<1> IFS0<2> IFS0<3> IFS0<4> IFS0<5> IFS0<6> IFS0<7> IFS0<8> IFS0<9> IFS0<10> IFS0<11> IFS0<12> IFS0<13> IFS0<14> IFS0<15> IFS0<16> IFS0<17> IFS0<18> IFS0<19> IFS0<20> IFS0<21> IFS0<22> IFS0<23> IFS0<24> IFS0<25> IFS0<26> IFS0<27> IFS0<28> IFS0<29> IFS0<30> IFS0<31> IFS1<0> IFS1<1> IFS1<2> IFS1<3> IFS1<4> Interrupt Bit Location Enable IEC0<0> IEC0<1> IEC0<2> IEC0<3> IEC0<4> IEC0<5> IEC0<6> IEC0<7> IEC0<8> IEC0<9> IEC0<10> IEC0<11> IEC0<12> IEC0<13> IEC0<14> IEC0<15> IEC0<16> IEC0<17> IEC0<18> IEC0<19> IEC0<20> IEC0<21> IEC0<22> IEC0<23> IEC0<24> IEC0<25> IEC0<26> IEC0<27> IEC0<28> IEC0<29> IEC0<30> IEC0<31> IEC1<0> IEC1<1> IEC1<2> IEC1<3> IEC1<4> Priority IPC0<4:2> IPC0<12:10> IPC0<20:18> IPC0<28:26> IPC1<4:2> IPC1<12:10> IPC1<20:18> IPC1<28:26> IPC2<4:2> IPC2<12:10> IPC2<20:18> IPC2<28:26> IPC3<4:2> IPC3<12:10> IPC3<20:18> IPC3<28:26> IPC4<4:2> IPC4<12:10> IPC4<20:18> IPC4<28:26> IPC5<4:2> IPC5<12:10> IPC5<20:18> IPC5<28:26> IPC5<28:26> IPC5<28:26> IPC6<4:2> IPC6<4:2> IPC6<4:2> IPC6<12:10> IPC6<12:10> IPC6<12:10> IPC6<20:18> IPC6<28:26> IPC7<4:2> IPC7<12:10> IPC7<20:18> Subpriority IPC0<1:0> IPC0<9:8> IPC0<17:16> IPC0<25:24> IPC1<1:0> IPC1<9:8> IPC1<17:16> IPC1<25:24> IPC2<1:0> IPC2<9:8> IPC2<17:16> IPC2<25:24> IPC3<1:0> IPC3<9:8> IPC3<17:16> IPC3<25:24> IPC4<1:0> IPC4<9:8> IPC4<17:16> IPC4<25:24> IPC5<1:0> IPC5<9:8> IPC5<17:16> IPC5<25:24> IPC5<25:24> IPC5<25:24> IPC6<1:0> IPC6<1:0> IPC6<1:0> IPC6<9:8> IPC6<9:8> IPC6<9:8> IPC6<17:16> IPC6<25:24> IPC7<1:0> IPC7<9:8> IPC7<17:16> Interrupt Source(1)
Highest Natural Order Priority CT - Core Timer Interrupt CS0 - Core Software Interrupt 0 CS1 - Core Software Interrupt 1 INT0 - External Interrupt 0 T1 - Timer1 IC1 - Input Capture 1 OC1 - Output Compare 1 INT1 - External Interrupt 1 T2 - Timer2 IC2 - Input Capture 2 OC2 - Output Compare 2 INT2 - External Interrupt 2 T3 - Timer3 IC3 - Input Capture 3 OC3 - Output Compare 3 INT3 - External Interrupt 3 T4 - Timer4 IC4 - Input Capture 4 OC4 - Output Compare 4 INT4 - External Interrupt 4 T5 - Timer5 IC5 - Input Capture 5 OC5 - Output Compare 5 SPI1E - SPI1 Fault SPI1TX - SPI1 Transfer Done SPI1RX - SPI1 Receive Done U1E - UART1 Error U1RX - UART1 Receiver U1TX - UART1 Transmitter I2C1B - I2C1 Bus Collision Event I2C1S - I2C1 Slave Event I2C1M - I2C1 Master Event CN - Input Change Interrupt AD1 - ADC1 Convert Done PMP - Parallel Master Port CMP1 - Comparator Interrupt CMP2 - Comparator Interrupt Note 1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX General Purpose - Features" and TABLE 2: "PIC32MX USB - Features" for available peripherals.
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PIC32MX3XX/4XX
TABLE 7-1: INTERRUPT IRQ AND VECTOR LOCATION (CONTINUED)
IRQ Vector Number Flag 31 31 31 32 32 32 33 33 33 34 35 36 37 38 39 44 45 IFS1<5> IFS1<6> IFS1<7> IFS1<8> IFS1<9> IFS1<10> IFS1<11> IFS1<12> IFS1<13> IFS1<14> IFS1<15> IFS1<16> IFS1<17> IFS1<18> IFS1<19> IFS1<24> IFS1<25> Interrupt Bit Location Enable IEC1<5> IEC1<6> IEC1<7> IEC1<8> IEC1<9> IEC1<10> IEC1<11> IEC1<12> IEC1<13> IEC1<14> IEC1<15> IEC1<16> IEC1<17> IEC1<18> IEC1<19> IEC1<24> IEC1<25> Priority IPC7<28:26> IPC7<28:26> IPC7<28:26> IPC8<4:2> IPC8<4:2> IPC8<4:2> IPC8<12:10> IPC8<12:10> IPC8<12:10> IPC8<20:18> IPC8<28:26> IPC9<4:2> IPC9<12:10> IPC9<20:18> IPC9<28:26> IPC11<4:2> IPC11<12:10> Subpriority IPC7<25:24> IPC7<25:24> IPC7<25:24> IPC8<1:0> IPC8<1:0> IPC8<1:0> IPC8<9:8> IPC8<9:8> IPC8<9:8> IPC8<17:16> IPC8<25:24> IPC9<1:0> IPC9<9:8> IPC9<17:16> IPC9<25:24> IPC11<1:0> IPC11<9:8> Interrupt Source(1)
Highest Natural Order Priority SPI2E - SPI2 Fault SPI2TX - SPI2 Transfer Done SPI2RX - SPI2 Receive Done U2E - UART2 Error U2RX - UART2 Receiver U2TX - UART2 Transmitter I2C2B - I2C2 Bus Collision Event I2C2S - I2C2 Slave Event I2C2M - I2C2 Master Event FSCM - Fail-Safe Clock Monitor RTCC - Real-Time Clock and Calendar DMA0 - DMA Channel 0 DMA1 - DMA Channel 1 DMA2 - DMA Channel 2 DMA3 - DMA Channel 3 FCE - Flash Control Event USB Note 1: 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 56 57
Lowest Natural Order Priority Not all interrupt sources are available on all devices. See TABLE 1: "PIC32MX General Purpose - Features" and TABLE 2: "PIC32MX USB - Features" for available peripherals.
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NOTES:
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PIC32MX3XX/4XX
8.0 OSCILLATOR CONFIGURATION
The PIC32MX oscillator system has the following modules and features: * A total of four external and internal oscillator options as clock sources * On-chip PLL (phase-locked loop) with userselectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources * On-chip user-selectable divisor postscaler on select oscillator sources * Software-controllable switching between various clock sources * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shut down * Dedicated on-chip PLL for USB peripheral
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the "PIC32 Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112), which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 8-1:
PIC32MX3XX/4XX FAMILY CLOCK DIAGRAM
USB PLL UFIN USB Clock (48 MHz) PLL x24 div 2 UFRCEN UPLLEN XT, HS, EC RF(2) To Internal Logic Enable 4 MHz FIN 5 MHz XTPLL, HSPLL, FIN ECPLL, FRCPLL div x div y PLL PLL Input Divider FPLLIDIV<2:0> FRC Oscillator 8 MHz typical TUN<5:0> Postscaler FRCDIV<2:0> LPRC Oscillator LPRC 31.25 kHz typical COSC<2:0> PLL Output Divider PLLODIV<2:0> Postscaler Peripherals div x PBCLK
div x Primary Oscillator (POSC) C1(3) OSC1
UFIN = 4 MHz UPLLIDIV<2:0>
XTAL RS
(1)
C2(3)
OSC2(4)
PBDIV<1:0>
PLL Multiplier PLLMULT<2:0>
FRC FRC/16 FRCDIV CPU and Select Peripherals SYSCLK
div 16
Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSCEN and FSOSCEN SOSCI Notes: 1. 2. 3. A series resistor, RS, may be required for AT strip-cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 M. Refer to the "PIC32 Family Reference Manual" Section 6. "Oscillator Configuration" (DS61112) for help determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. SOSC
Clock Control Logic Fail-Safe Clock Monitor FSCM INT FSCM Event
NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT
4.
Timer1, RTCC
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NOTES:
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PIC32MX3XX/4XX
9.0 PREFETCH CACHE
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. "Prefetch Cache" (DS61119) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching.
9.1
* * * * * * * *
Features
16 Fully Associative Lockable Cache Lines 16-byte Cache Lines Up to four Cache Lines Allocated to Data Two Cache Lines with Address Mask to hold repeated instructions Pseudo LRU replacement policy All Cache Lines are software writable 16-byte parallel memory fetch Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
FSM Tag Logic CTRL Cache Line BMX/CPU Cache Line Address Encode RDATA Hit Logic Prefetch Prefetch RDATA PFM DS61143H-page 95
BMX/CPU
CTRL
Bus Control Cache Control Prefetch Control Hit LRU Miss LRU
CTRL
(c) 2011 Microchip Technology Inc.
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NOTES:
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PIC32MX3XX/4XX
10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER
* Automatic Word-Size Detection: - Transfer Granularity, down to byte level - Bytes need not be word-aligned at source and destination * Fixed Priority Channel Arbitration * Flexible DMA Channel Operating Modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining * Flexible DMA Requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination * Multiple DMA Channel Status Interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half-full - DMA transfer aborted due to an external event - Invalid DMA address generated * DMA Debug Support Features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data * CRC Generation Module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. "Direct Memory Access (DMA) Controller" (DS61117) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32MX (such as Peripheral Bus (PBUS) devices: SPI, UART, PMP, and so on) or memory itself. Following are some of the key features of the DMA controller module: * Four Identical Channels, each featuring: - Auto-Increment Source and Destination Address Registers - Source and Destination Pointers - Memory to Memory and Memory to Peripheral Transfers
FIGURE 10-1:
INT Controller
DMA BLOCK DIAGRAM
System IRQ
Peripheral Bus
Address Decoder
Channel 0 Control
SE
L
I0
Channel 1 Control
I1 I2
Y
Bus Interface
Device Bus + Bus Arbitration
Global Control (DMACON)
Channel n Control
In
SE L
Channel Priority Arbitration
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NOTES:
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PIC32MX3XX/4XX
11.0 USB ON-THE-GO (OTG)
The PIC32MX USB module includes the following features: * * * * * * * * * USB Full-Speed Support for Host and Device Low-Speed Host Support USB OTG Support Integrated Signaling Resistors Integrated Analog Comparators for VBUS Monitoring Integrated USB Transceiver Transaction Handshaking Performed by Hardware Endpoint Buffering Anywhere in System RAM Integrated DMA to Access System RAM and Flash Note: The implementation and use of the USB specifications, as well as other third-party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. "USB OnThe-Go (OTG)" (DS61126) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 fullspeed and low-speed embedded host, full-speed device, or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32MX USB OTG module is presented in Figure 11-1. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module.
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FIGURE 11-1: PIC32MX3XX/4XX FAMILY USB INTERFACE DIAGRAM
USBEN USB Suspend CPU Clock Not POSC Sleep Primary Oscillator (POSC) Div x OSC1 UPLLIDIV(6) USB Suspend OSC2 (PB out)(1)
FRC Oscillator 8 MHz Typical TUN<5:0>(4)
UFIN(5) PLL Div 2 UFRCEN(3) UPLLEN(6) To Clock Generator for Core and Peripherals Sleep or Idle
USB Module
SRP Charge VBUS SRP Discharge USB Voltage Comparators 48 MHz USB Clock(7)
Full Speed Pull-up D+(2) Registers and Control Interface SIE Transceiver Low Speed Pull-up
Host Pull-down
D-(2) DMA Host Pull-down System RAM
ID Pull-up ID(8) VBUSON(8)
VUSB
Transceiver Power 3.3V
Note
1: 2: 3: 4: 5: 6: 7: 8:
PB clock is only available on this pin for select EC modes. Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled.
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PIC32MX3XX/4XX
12.0 I/O PORTS
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. "I/O Ports" (DS61120) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. General purpose I/O pins are the simplest of peripherals. They allow the PIC(R) MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Following are some of the key features of this module: * Individual Output Pin Open-drain Enable/Disable * Individual Input Pin Weak Pull-up Enable/Disable * Monitor Selective Inputs and Generate Interrupt when Change in Pin State is Detected * Operation during CPU Sleep and Idle modes * Fast Bit Manipulation using CLR, SET and INV Registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data
PIO Module RD ODC
Data Bus SYSCLK WR ODC RD TRIS
D
Q
ODC CK EN Q 1 0 0 1 D Q 1 0 Output Multiplexers D Q I/O Pin LAT CK EN Q TRIS CK EN Q I/O Cell
WR TRIS
WR LAT WR PORT RD LAT 1 RD PORT 0 Sleep SYSCLK Synchronization Peripheral Input Peripheral Input Buffer Legend: Note: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. R Q Q D CK Q Q D CK
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12.1 Parallel I/O (PIO) Ports
All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a data direction or tri-state control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1 configures the corresponding I/O pin as an input; setting a TRISx register bit = 0 configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset. Certain I/O pins are shared with analog peripherals and default to analog inputs after a device Reset. PORT is a register used to read the current state of the signal applied to the port I/O pins. Writing to a PORTx register performs a write to the port's latch, LATx register, latching the data to the port's I/O pins. LAT is a register used to write data to the port I/O pins. The LATx latch register holds the data written to either the LATx or PORTx registers. Reading the LATx latch register reads the last value written to the corresponding port or latch register. Not all port I/O pins are implemented on some devices, therefore, the corresponding PORTx, LATx and TRISx register bits will read as zeros. The maximum input voltage allowed on the input pins is the same as the maximum VIH specification. Refer to Section 29.0 "Electrical Characteristics" for VIH specification details. Note: Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications.
12.1.3
ANALOG INPUTS
Certain pins can be configured as analog inputs used by the ADC and Comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is cleared = 0 (output), the digital output level (VOH or VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the corresponding PORTx register bit will read `0'. The AD1PCFG Register has a default value of 0x0000; therefore, all pins that share ANx functions are analog (not digital) by default.
12.1.4
DIGITAL OUTPUTS
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as `1' are modified. Bits specified as `0' are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. Note: Using a PORTxINV register to toggle a bit is recommended because the operation is performed in hardware atomically, using fewer instructions as compared to the traditional read-modify-write method shown below: PORTC ^= 0x0001;
Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration register. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the "Pin Diagrams" section for the available pins and their functionality.
12.1.5
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such as the CVREF output voltage used by the comparator module. Configuring the Comparator Reference module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin.
12.1.2
DIGITAL INPUTS
12.1.6
INPUT CHANGE NOTIFICATION
Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are either TTL buffers or Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at POR. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin.
The input change notification function of the I/O ports (CNx) allows devices to generate interrupt requests in response to change of state on selected pin. Each CNx pin also has a weak pull-up, which acts as a current source connected to the pin. The pull-ups are enabled by setting corresponding bit in CNPUE register.
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13.0 TIMER1
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS61105) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. This family of PIC32MX devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Secondary Oscillator (SOSC) for real-time clock applications. The following modes are supported: * * * * Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer
13.1
Additional Supported Features
* Selectable clock prescaler * Timer operation during CPU Idle and Sleep mode * Fast bit manipulation using CLR, SET and INV registers * Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC)
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM(1)
PR1 Equal
16-bit Comparator
TSYNC (T1CON<2>) 1 Sync
TMR1 Reset T1IF Event Flag 0 1 TGATE (T1CON<7>) Q Q D TGATE (T1CON<7>) TCS (T1CON<1>) ON (T1CON<15>) 0
SOSCO/T1CK SOSCEN SOSCI PBCLK Gate Sync
x1 Prescaler 1, 8, 64, 256
10 00
2 TCKPS<1:0> (T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1.
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NOTES:
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14.0 TIMER2/3 AND TIMER4/5
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. "Timers" (DS61105) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. This family of PIC32MX devices features four synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: * Synchronous Internal 16-bit Timer * Synchronous Internal 16-bit Gated Timer * Synchronous External 16-bit Timer Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: * Synchronous Internal 32-bit Timer * Synchronous Internal 32-bit Gated Timer * Synchronous External 32-bit Timer Note: Throughout this chapter, references to registers TxCON, TMRx and PRx use `x' to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, `x' represents Timer2 or 4; `y' represents Timer3 or 5.
14.1
Additional Supported Features
* Selectable clock prescaler * Timers operational during CPU Idle * Time base for input capture and output compare modules (Timer2 and Timer3 only) * ADC event trigger (Timer3 only) * Fast bit manipulation using CLR, SET and INV registers
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
TMRx Sync
ADC Event Trigger(1)
Equal
Comparator x 16
PRx Reset 0 1 TGATE (TxCON<7>) Q Q D TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) TxCK(2) Gate Sync PBCLK Note 1: ADC event trigger is available on Timer3 only. 2: TxCK pins not available on 64-pin devices.
TxIF Event Flag
x1 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>)
10 00
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FIGURE 14-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)
Reset TMRy MSHalfWord ADC Event Trigger(3) Equal TMRx LSHalfWord Sync
32-bit Comparator
PRy TyIF Event Flag 0 1 TGATE (TxCON<7>)
PRx
Q Q
D
TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>)
TxCK(2) Gate Sync PBCLK
x1 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>)
10 00
Note 1: In this diagram, the use of `x' in registers TxCON, TMRx, PRx and TxCK refers to either Timer2 or Timer4; the use of `y' in registers TyCON, TMRy, PRy and TyIF refers to either Timer3 or Timer5. 2: TxCK pins are not available on 64-pin devices. 3: ADC event trigger is available only on Timer2/3 pair.
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15.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. "Input Capture" (DS61122) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC32MX3XX/4XX devices support up to five input capture channels. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: 1. Simple Capture Event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler Capture Event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: * Device wake-up from capture pin during CPU Sleep and Idle modes * Interrupt on input capture event * 4-word FIFO buffer for capture values - Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled * Input capture can also be used to provide additional sources of external interrupts 2.
FIGURE 15-1:
INPUT CAPTURE BLOCK DIAGRAM
ICx Input ICTMR 0 C32 FIFO Control ICxBUF<31:16> ICxBUF<15:0> 1 Timer3 Timer2
Prescaler 1, 4, 16
Edge Detect
ICM<2:0>
ICM<2:0> FEDGE
ICBNE ICOV Interrupt Event Generation Data Space Interface
ICxCON
ICI<1:0>
Interrupt
Peripheral Data Bus
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16.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. "Output Compare" (DS61111) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. The following are some of the key features: * Multiple output compare modules in a device * Programmable interrupt generation on compare event * Single and Dual Compare modes * Single and continuous output pulse generation * Pulse-Width Modulation (PWM) mode * Hardware-based PWM Fault detection and automatic output disable * Programmable selection of 16-bit or 32-bit time bases. * Can operate from either of two available 16-bit time bases or a single 32-bit time base
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
OCxR(1)
Output Logic 3 OCM<2:0> Mode Select
S R
Q
OCx(1)
Comparator
Output Enable
Output Enable Logic
OCFA or OCFB (see Note 2) 0 1 OCTSEL 0 1
16
16
TMR register inputs from time bases (see Note 3)
Period match signals from time bases (see Note 3)
Note 1: Where `x' is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. 3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
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17.0 SERIAL PERIPHERAL INTERFACE (SPI)
The SPI module is a synchronous serial interface useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, Analog-to-Digital Converters, etc. The PIC32MX SPI module is compatible with Motorola(R) SPI and SIOP interfaces. Following are some of the key features of this module: * * * * * * * * Master and Slave Modes Support Four Different Clock Formats Framed SPI Protocol Support User Configurable 8-bit, 16-bit and 32-bit Data Width Separate SPI Data Registers for Receive and Transmit Programmable Interrupt Event on every 8-bit, 16-bit and 32-bit Data Transfer Operation during CPU Sleep and Idle Mode Fast Bit Manipulation using CLR, SET and INV Registers
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. "Serial Peripheral Interface (SPI)" (DS61106) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
Internal Data Bus
SPIxBUF Read Write Registers share address SPIxBUF SPIxRXB SPIxTXB Transmit
Receive SPIxSR SDIx bit 0
SDOx Slave Select and Frame Sync Control
Shift Control Clock Control Edge Select Baud Rate Generator
SSx/FSYNC
PBCLK
SCKx Enable Master Clock Note: Access SPIxTXB and SPIxRXB registers via SPIxBUF register.
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18.0 INTER-INTEGRATED CIRCUITTM (I2CTM)
The PIC32MX3XX/4XX devices have up to two I2C interface modules, denoted as I2C1 and I2C2. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module, `I2Cx' (x = 1 or 2), offers the following key features: * I2C Interface Supporting both Master and Slave Operation. * I2C Slave Mode Supports 7 and 10-bit Address. * I2C Master Mode Supports 7 and 10-bit Address. * I2C Port allows Bidirectional Transfers between Master and Slaves. * Serial Clock Synchronization for I2C Port can be used as a Handshake Mechanism to Suspend and Resume Serial Transfer (SCLREL control). * I2C Supports Multi-master Operation; Detects Bus Collision and Arbitrates Accordingly. * Provides Support for Address Bit Masking.
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. "Inter-Integrated Circuit (I2CTM)" (DS61116) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 18-1 illustrates the I2C module block diagram.
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FIGURE 18-1: I2CTM BLOCK DIAGRAM (X = 1 OR 2)
Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Match Detect Address Match
Write I2CxMSK Write Read
I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Read Write
Collision Detect
I2CxCON Read
Acknowledge Generation Clock Stretching
Write
I2CxTRN LSB Shift Clock Reload Control Read
Write I2CxBRG Read
BRG Down Counter
PBCLK
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19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. "Universal Asynchronous Receiver Transmitter (UART)" (DS61107) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The UART module is one of the serial I/O modules available in PIC32MX3XX/4XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols such as RS232, RS-485, LIN 1.2 and IrDA(R). The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. The primary features of the UART module are: * * * * * * * * * * * * * Full-duplex, 8-bit or 9-bit data transmission Even, odd or no parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 76 bps to 20 Mbps at 80 MHz 4-level-deep First-In-First-Out (FIFO) Transmit Data Buffer 4-level-deep FIFO Receive Data Buffer Parity, framing and buffer overrun error detection Support for interrupt only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support
Note
* LIN protocol support * IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 19-1 illustrates a simplified block diagram of the UART.
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA(R)
BCLKx
UxRTS Hardware Flow Control UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
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FIGURE 19-2: TRANSMISSION (8-BIT OR 9-BIT DATA)
Write to UxTXREG BCLK/16 (Shift Clock) UxTX Character 1
Start bit
bit 0
bit 1 Character 1
bit 7/8
Stop bit
UxTXIF Character 1 to Transmit Shift Register TRMT bit
UxTXIF Cleared by User
FIGURE 19-3:
TWO CONSECUTIVE TRANSMISSIONS
Write to UxTXREG BCLK/16 (Shift Clock) UxTX Character 1 Character 2
Start bit
bit 0
bit 1 Character 1
bit 7/8
Stop bit
Start bit bit 0 Character 2
UxTXIF (UTXISEL0 = 0) UxTXIF (UTXISEL0 = 1)
UxTXIF Cleared by User in Software
Character 1 to Transmit Shift Register TRMT bit
Character 2 to Transmit Shift Register
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FIGURE 19-4: UART RECEPTION
Start bit bit 0 Start bit bit 0
UxRX UxRXIF (RXISEL = 0x)
bit1
bit 7 Stop bit
bit 7 Stop bit
Character 1 to UxRXREG RIDLE bit
Character 2 to UxRXREG
Note:
This timing diagram shows 2 characters received on the UxRX input.
FIGURE 19-5:
UART RECEPTION WITH RECEIVE OVERRUN
Character 1 Characters 2, 3, 4, 5 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Character 6 Start bit bit 7/8 Stop bit
UxRX
Start bit bit 0 bit 1
Character 1, 2, 3, 4 Stored in Receive FIFO OERR bit
Character 5 Held in UxRSR OERR Cleared by User
RIDLE bit
Note:
This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the Receive Shift register. An overrun error occurs at the start of the 6th character.
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20.0 PARALLEL MASTER PORT (PMP)
Key features of the PMP module include: * * * * 8-bit,16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options - Individual read and write strobes, or - Read/write strobe with enable strobe Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Slave Port support - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait states Operate during CPU Sleep and Idle modes Fast bit manipulation using CLR, SET and INV registers Freeze option for in-circuit debugging Note: On 64-pin devices, data pins PMD<15:8> are not available.
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. "Parallel Master Port (PMP)" (DS61128) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable.
* * * *
* * * *
FIGURE 20-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus Data Bus Control Lines
PIC32MX3XX/4XX Parallel Master Port
PMA<0> PMALL PMA<1> PMALH
Up to 16-bit Address
PMA<13:2> PMA<14> PMCS1 PMA<15> PMCS2
FLASH EEPROM SRAM
PMRD PMRD/PMWR PMWR PMENB
Microcontroller
LCD
FIFO buffer
PMD<7:0> PMD<15:8>(1)
16/8-bit Data (with or without multiplexed addressing)
Note 1:
On 64-pin devices, data pins PMD<15:8> are not available in 16-bit Master modes.
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21.0 REAL-TIME CLOCK AND CALENDAR (RTCC)
The following are some of the key features of this module: * * * * * Time: Hours, Minutes and Seconds 24-Hour Format (Military Time) Visibility of One-Half-Second Period Provides Calendar: Weekday, Date, Month and Year Alarm Intervals are configurable for Half of a Second, One Second, 10 Seconds, One Minute, 10 Minutes, One Hour, One Day, One Week, One Month and One Year Alarm Repeat with Decrementing Counter Alarm with Indefinite Repeat: Chime Year Range: 2000 to 2099 Leap Year Correction BCD Format for Smaller Firmware Overhead Optimized for Long-Term Battery Operation Fractional Second Synchronization User Calibration of the Clock Crystal Frequency with Auto-Adjust Calibration Range: 0.66 Seconds Error per Month Calibrates up to 260 ppm of Crystal Error Requirements: External 32.768 kHz Clock Crystal Alarm Pulse or Seconds Clock Output on RTCC pin
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. "Real-Time Clock and Calendar (RTCC)" (DS61125) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time.
* * * * * * * * * * * *
FIGURE 21-1:
RTCC BLOCK DIAGRAM
32.768 kHz Input from Secondary Oscillator (SOSC)
RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL YEAR, MTH, DAY WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks Repeat Counter ALRMVAL WKDAY HR, MIN, SEC
RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse RTCC Pin
RTCOE
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22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
* * * * * * Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Eight conversion result format options Operation during CPU Sleep and Idle modes
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS61104) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX3XX/4XX 10-bit Analog-to-Digital Converter (ADC) includes the following features: * Successive Approximation Register (SAR) conversion * Up to 1000 kilo samples per second (ksps) conversion speed * Up to 16 analog input pins * External voltage reference input pins * One unipolar, differential Sample-and-Hold Amplifier (SHA)
A block diagram of the 10-bit ADC is illustrated in Figure 22-1. The 10-bit ADC has 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 22-1). The Analog Input Scan mode sequentially converts user-specified channels. A control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight, 32-bit output formats when it is read from the result buffer.
FIGURE 22-1:
ADC1 MODULE BLOCK DIAGRAM
VREF+(1) AVDD VREF-(1) AVSS
VCFG<2:0> AN0 AN15 ADC1BUF0 ADC1BUF1 ADC1BUF2 VREFH SAR ADC VREFL
CHANNEL SCAN
CH0SA<4:0> CSCNA AN1 VREFL CH0SB<4:0>
S/H + -
ADC1BUFE ADC1BUFF CH0NA CH0NB
Alternate Input Selection
Note
1:
VREF+, VREF- inputs can be multiplexed with other analog inputs.
(c) 2011 Microchip Technology Inc.
DS61143H-page 123
PIC32MX3XX/4XX
FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
ADC Internal RC Clock(1) ADCS<7:0> 8 ADC Conversion Clock Multiplier 2,4,..., 512
1
TAD
0
TPB
Note
1:
See the ADC electrical characteristics for the exact RC clock value.
DS61143H-page 124
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
23.0 COMPARATOR
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 19. "Comparator" (DS61110) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. The PIC32MX3XX/4XX Analog Comparator module contains one or more comparator(s) that can be configured in a variety of ways. Following are some of the key features of this module: * Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) * Outputs can be inverted * Selectable interrupt generation A block diagram of the comparator module is illustrated in Figure 23-1.
FIGURE 23-1:
COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF ON CPOL COUT (CM1CON) C1OUT (CMSTAT)
C1IN+(1) CVREF(2) CCH<1:0> C1INC1IN+ C2IN+ IVREF(2) C1
C1OUT
COE
Comparator 2
CREF C2IN+ CVREF(2) CCH<1:0> C2INC2IN+ C1IN+ IVREF(2) COE C2 ON CPOL COUT (CM2CON) C2OUT (CMSTAT)
C2OUT
Note 1: 2:
On USB variants, when USB is enabled, this pin is controlled by the USB module and therefore is not available as a comparator input. Internally connected.
(c) 2011 Microchip Technology Inc.
DS61143H-page 125
PIC32MX3XX/4XX
NOTES:
DS61143H-page 126
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
24.0 COMPARATOR VOLTAGE REFERENCE (CVREF)
The CVREF is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. A block diagram of the module is illustrated in Figure 24-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. The comparator voltage reference has the following features: * High and low range selection * Sixteen output levels available for each range * Internally connected to comparators to conserve device pins * Output can be connected to a pin
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. Refer to Section 20. "Comparator Voltage Reference (CVREF)" (DS61109) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information.
FIGURE 24-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD
CVRSS = 1
CVRSS = 0
8R R R R R 16 Steps
CVR3:CVR0
CVREN
CVREF
16-to-1 MUX
CVREFOUT CVRCON
R R R
CVRR VREFAVSS CVRSS = 1
8R
CVRSS = 0
(c) 2011 Microchip Technology Inc.
DS61143H-page 127
PIC32MX3XX/4XX
NOTES:
DS61143H-page 128
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
25.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features of the PIC32MX3XX/4XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. "Power-Saving Features" (DS61130) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 "Memory Organization" in this data sheet for device-specific register and bit information. This section describes power-saving for the PIC32MX3XX/4XX. The PIC32MX devices offer a total of nine methods and modes that are organized into two categories that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, power-saving is controlled by software. * LPRC Idle Mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. * Sleep Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device.
25.3
Power-Saving Operation
The purpose of all power-saving is to reduce power consumption by reducing the device clock frequency. To achieve this, low-frequency clock sources can be selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power consumption.
25.3.1
SLEEP MODE
25.1
Power-Saving with CPU Running
When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK, and by individually disabling modules. These methods are grouped into the following modes: * FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. * LPRC Run mode: the CPU is clocked from the LPRC clock source. * SOSC Run mode: the CPU is clocked from the SOSC clock source. * Peripheral Bus Scaling mode: peripherals are clocked at programmable fraction of the CPU clock (SYSCLK).
Sleep mode has the lowest power consumption of the device Power-Saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep mode. Sleep mode includes the following characteristics: * The CPU is halted. * The system clock source is typically shut down. See Section 25.3.2 "Idle Mode" for specific information. * There can be a wake-up delay based on the oscillator selection. * The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. * The BOR circuit, if enabled, remains operative during Sleep mode. * The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. * Some peripherals can continue to operate in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator, e.g., RTCC and Timer 1. * I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. * The USB module can override the disabling of the POSC or FRC. Refer to Section 11.0 "USB OnThe-Go (OTG)" for specific details. * Some modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption.
25.2
CPU Halted Methods
The device supports two power-saving modes, Sleep and Idle, both of which halt the clock to the CPU. These modes operate with all clock sources, as listed below: * POSC Idle Mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. * FRC Idle Mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. * SOSC Idle Mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled.
(c) 2011 Microchip Technology Inc.
DS61143H-page 129
PIC32MX3XX/4XX
The processor will exit, or `wake-up', from Sleep on one of the following events: * On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. * On any form of device Reset. * On a WDT time-out. See Section 26.2 "Watchdog Timer (WDT)". If the interrupt priority is lower than or equal to current priority, the CPU will remain halted, but the PBCLK will start running and the device will enter into Idle mode. Note: There is no FRZ mode for this module. The processor will wake or exit from Idle mode on the following events: * On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU will remain halted and the device will remain in Idle mode. * On any source of device Reset. * On a WDT time-out interrupt. See Section 26.2 "Watchdog Timer (WDT)".
25.3.3 25.3.2 IDLE MODE
In the Idle mode, the CPU is halted but the System clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is halted. Peripherals can be individually configured to halt when entering Idle by setting their respective SIDL bit. Latency when exiting Idle mode is very low due to the CPU oscillator source remaining active. Note: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in PB divisor ratio. Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator startup/lock delays would be applied. The device enters Idle mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed.
PERIPHERAL BUS SCALING METHOD
Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, Interrupt Controller, DMA, Bus Matrix and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes Changing the PBCLK divisor affects: * The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode this results in a latency of one to seven SYSCLKs. * The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value.
DS61143H-page 130
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
26.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of the PIC32MX3XX/4XX family family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. "Watchdog Timer and Power-up Timer" (DS61114), Section 32. "Configuration" (DS61124) and Section 33. "Programming and Diagnostics" (DS61129) of the "PIC32 Family Reference Manual", which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX3XX/4XX devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are: * * * * Flexible Device Configuration Watchdog Timer JTAG Interface In-Circuit Serial ProgrammingTM (ICSPTM)
26.1
Configuration Bits
The Configuration bits can be programmed to select various device configurations.
REGISTER 26-1:
Bit Range 31:24 23:16 15:8 7:0
DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit 30/22/14/6
r-1
Bit 31/23/15/7
r-0
Bit 29/21/13/5
r-1
Bit 28/20/12/4
R/P
Bit 27/19/11/3
r-1
Bit 26/18/10/2
r-1
Bit 25/17/9/1
r-1
Bit 24/16/8/0
R/P
--
r-1
--
r-1
--
r-1
CP
r-1
--
R/P
--
R/P
--
R/P
BWP
R/P
--
R/P
--
R/P
--
R/P
--
R/P r-1 r-1
PWP<7:4>
r-1 r-1
PWP<3:0>
r-1 r-1 r-1 r-1
--
R/P
--
r-1
--
R/P
--
R/P
--
--
--
--
ICESEL
--
DEBUG<1:0>
Legend: R = Readable bit U = Unimplemented bit bit 31 bit 28 Reserved: Write `0' CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection disabled 0 = Protection enabled BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown)
bit 30-29 Reserved: Write `1'
bit 27-25 Reserved: Write `1' bit 24
bit 23-20 Reserved: Write `1'
(c) 2011 Microchip Technology Inc.
DS61143H-page 131
PIC32MX3XX/4XX
REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. The PWP bits represent the one's compliment of the number of write protected program Flash memory pages. 11111111 = Disabled 11111110 = 0xBD00_0FFF 11111101 = 0xBD00_1FFF 11111100 = 0xBD00_2FFF 11111011 = 0xBD00_3FFF 11111010 = 0xBD00_4FFF 11111001 = 0xBD00_5FFF 11111000 = 0xBD00_6FFF 11110111 = 0xBD00_7FFF 11110110 = 0xBD00_8FFF 11110101 = 0xBD00_9FFF 11110100 = 0xBD00_AFFF 11110011 = 0xBD00_BFFF 11110010 = 0xBD00_CFFF 11110001 = 0xBD00_DFFF 11110000 = 0xBD00_EFFF 11101111 = 0xBD00_FFFF . . . 01111111 = 0xBD07_FFFF bit 11-4 bit 3 Reserved: Write `1' ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used Reserved: Write `1' DEBUG<1:0>: Background Debugger Enable bits (forced to `11' if code-protect is enabled) 11 = Debugger disabled 10 = Debugger enabled 01 = Reserved (same as `11' setting) 00 = Reserved (same as `11' setting)
bit 2 bit 1-0
DS61143H-page 132
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 26-2:
Bit Range 31:24 23:16 15:8 7:0
DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit 30/22/14/6
r-1
Bit 31/23/15/7
r-1
Bit 29/21/13/5
r-1
Bit 28/20/12/4
r-1
Bit 27/19/11/3
r-1
Bit 26/18/10/2
r-1
Bit 25/17/9/1
r-1
Bit 24/16/8/0
r-1
--
R/P
--
r-1
--
r-1
--
R/P
--
R/P
--
R/P
--
R/P
--
R/P
FWDTEN
R/P
--
R/P
--
R/P R/P r-1
WDTPS<4:0>
R/P R/P R/P
FCKSM<1:0>
R/P r-1
FPBDIV<1:0>
R/P r-1
--
r-1
OSCIOFNC
R/P
POSCMOD<1:0>
R/P R/P
IESO
--
FSOSCEN
--
--
FNOSC<2:0>
Legend: R = Readable bit U = Unimplemented bit bit 31-24 Reserved: Write `1' bit 23 FWDTEN: Watchdog Timer Enable bit 1 = The WDT is enabled and cannot be disabled by software 0 = The WDT is not enabled; it can be enabled in software W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown)
bit 22-21 Reserved: Write `1' bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = `10100' bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Note 1: Do not disable POSC (POSCMOD = 00) when using this oscillator source.
(c) 2011 Microchip Technology Inc.
DS61143H-page 133
PIC32MX3XX/4XX
REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 bit 10 Reserved: Write `1' OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 OR 00) 0 = CLKO output disabled POSCMOD<1:0>: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) Reserved: Write `1' FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Reserved: Write `1' FNOSC<2:0>: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Do not disable POSC (POSCMOD = 00) when using this oscillator source.
bit 9-8
bit 7
bit 6 bit 5
bit 4-3 bit 2-0
Note 1:
DS61143H-page 134
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
REGISTER 26-3:
Bit Range 31:24 23:16 15:8 7:0
DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit 30/22/14/6
r-1
Bit 31/23/15/7
r-1
Bit 29/21/13/5
r-1
Bit 28/20/12/4
r-1
Bit 27/19/11/3
r-1
Bit 26/18/10/2
r-1
Bit 25/17/9/1
r-1
Bit 24/16/8/0
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
R/P R/P R/P
--
R/P
--
R/P R/P R/P
--
R/P
--
r-1
--
r-1
--
r-1
--
r-1
FPLLODIV<2:0>
R/P
UPLLEN
r-1
--
R/P
--
R/P
--
R/P
--
r-1
UPLLIDIV<2:0>
R/P
--
FPLLMUL<2:0>
--
FPLLIDIV<2:0>
Legend: R = Readable bit U = Unimplemented bit
W = Writable bit P = Programmable bit -n = Bit Value at POR: (`0', `1', x = Unknown)
r = Reserved bit
bit 31-19 Reserved: Write `1' bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit 1 = Disable and bypass USB PLL 0 = Enable USB PLL bit 14-11 Reserved: Write `1' bit 10-8 UPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 Reserved: Write `1' bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 Reserved: Write `1' bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider
(c) 2011 Microchip Technology Inc.
DS61143H-page 135
PIC32MX3XX/4XX
REGISTER 26-4:
Bit Range 31:24 23:16 15:8 7:0
DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit 30/22/14/6
r-1
Bit 31/23/15/7
r-1
Bit 29/21/13/5
r-1
Bit 28/20/12/4
r-1
Bit 27/19/11/3
r-1
Bit 26/18/10/2
r-1
Bit 25/17/9/1
r-1
Bit 24/16/8/0
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
r-1
--
R/P
--
R/P
--
R/P
--
R/P
--
R/P
--
R/P
--
R/P
--
R/P
USERID<15:8>
R/P R/P R/P R/P R/P R/P R/P R/P
USERID<7:0>
Legend: R = Readable bit U = Unimplemented bit bit 31-16 Reserved: Write `1' bit 15-0 USERID<15:0>: This is a 16-bit value that is user defined and is readable via ICSPTM and JTAG W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown)
REGISTER 26-5:
Bit Range 31:24 23:16 15:8 7:0
DEVID: DEVICE AND REVISION ID REGISTER
Bit 30/22/14/6
R
Bit 31/23/15/7
R
Bit 29/21/13/5
R
Bit 28/20/12/4
R
Bit 27/19/11/3
R
Bit 26/18/10/2
R
Bit 25/17/9/1
R (1) R
Bit 24/16/8/0
R
VER<3:0>(1)
R R R R
DEVID<27:24> DEVID<23:16>
R (1) R
R
R
R
R
R (1) DEVID<15:8> R R
R
R
R
R
R
R
R
R
R
R
DEVID<7:0>(1)
Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown)
bit 31-28 VER<3:0>: Revision Identifier bits(1) bit 27-0 Note 1: DEVID<27:0>: Device ID(1) See the "PIC32MX Flash Programming Specification" (DS61145) for a list of Revision and Device ID values.
DS61143H-page 136
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
26.2 Watchdog Timer (WDT)
This section describes the operation of the WDT and Power-Up Timer of the PIC32MX3XX/4XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: * Configuration or software controlled * User-configurable time-out period * Can wake the device from Sleep or Idle
FIGURE 26-1:
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
LPRC Control PWRT Enable 1:64 Output
1
PWRT Enable WDT Enable
LPRC Oscillator
PWRT
Clock 25-bit Counter WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event WDT Counter Reset 25 0 1 Power Save Decoder Device Reset NMI (Wake-up)
FWDTPS<4:0>(DEVCFG1<20:16>)
(c) 2011 Microchip Technology Inc.
DS61143H-page 137
PIC32MX3XX/4XX
26.3 On-Chip Voltage Regulator
26.3.1 ON-CHIP REGULATOR AND POR
All PIC32MX3XX/4XX device's core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX3XX/4XX incorporate an on-chip regulator providing the required core logic voltage from VDD. The internal 1.8V regulator is controlled by the ENVREG pin. Tying this pin to VDD enables the regulator, which in turn provides power to the core. A low ESR capacitor (such as tantalum) must be connected to the VCORE/VCAP pin (Figure 26-2). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor is provided in Section 29.1 "DC Characteristics". Note: It is important that the low ESR capacitor is placed as close as possible to the VCORE/VCAP pin. When the voltage regulator is enabled, it takes fixed delay for it to generate output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of TPWRT at device start-up. See Section 29.0 "Electrical Characteristics" for more information on TPU AND TPWRT.
26.3.2
ON-CHIP REGULATOR AND BOR
Tying the ENVREG pin to VSS disables the regulator. In this case, separate power for the core logic at a nominal 1.8V must be supplied to the device on the VCORE/VCAP pin. Alternatively, the VCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 26-2 for possible configurations.
When the on-chip regulator is enabled, PIC32MX3XX/4XX devices also have a simple brownout capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage levels are specific in Section 29.1 "DC Characteristics".
26.3.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VCORE must never exceed VDD by 0.3 volts.
FIGURE 26-2:
CONNECTIONS FOR THE ON-CHIP REGULATOR
Regulator Disabled (ENVREG tied to ground): 1.8V(1) PIC32MX VDD ENVREG VCORE/VCAP 3.3V(1) PIC32MX VDD ENVREG VCORE/VCAP VSS
Regulator Enabled (ENVREG tied to VDD): 3.3V
CEFC (10 F typ)
VSS
Note 1:
These are typical operating voltages. Refer to Section 29.1 "DC Characteristics" for the full operating ranges of VDD and VCORE.
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26.4 Programming and Diagnostics
PIC32MX3XX/4XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: * Simplified field programmability using two-wire InCircuit Serial ProgrammingTM (ICSPTM) interfaces * Debugging using ICSP * Programming and debugging capabilities using the EJTAG extension of JTAG * JTAG boundary scan testing for device and board diagnostics PIC32MX devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer.
FIGURE 26-3:
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
PGEC1 PGED1 ICSPTM Controller PGEC2 PGED2 ICESEL TDI TDO TCK TMS JTAGEN TRCLK TRD0 TRD1 TRD2 TRD3 DEBUG<1:0> Instruction Trace Controller DEBUG<1:0> JTAG Controller Core
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REGISTER 26-6:
Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7
r-x
DDPCON: DEBUG DATA PORT CONTROL REGISTER
Bit 30/22/14/6
r-x
Bit 29/21/13/5
r-x
Bit 28/20/12/4
r-x
Bit 27/19/11/3
r-x
Bit 26/18/10/2
r-x
Bit 25/17/9/1
r-x
Bit 24/16/8/0
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
r-x
--
R/W-0
--
R/W-0
--
R/W-0
--
R/W-0
--
R/W-1
--
R/W-0
--
r-x
--
r-x
DDPUSB
DDPU1
DDPU2
DDPSPI1
JTAGEN
TROEN
--
--
Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (`0', `1', x = Unknown)
bit 31-8 Reserved: Write `0'; ignore read bit 7 DDPUSB: Debug Data Port Enable for USB bit 1 = USB peripheral ignores USBFRZ (U1CNFG1<5>) setting 0 = USB peripheral follows USBFRZ setting DDPU1: Debug Data Port Enable for UART1 bit 1 = UART1 peripheral ignores FRZ (U1MODE<14>) setting 0 = UART1 peripheral follows FRZ setting DDPU2: Debug Data Port Enable for UART2 bit 1 = UART2 peripheral ignores FRZ (U2MODE<14>) setting 0 = UART2 peripheral follows FRZ setting DDPSPI1: Debug Data Port Enable for SPI1 bit 1 = SPI1 peripheral ignores FRZ (SPI1CON<14>) setting 0 = SPI1 peripheral follows FRZ setting JTAGEN: JTAG Port Enable bit 1 = Enable JTAG Port 0 = Disable JTAG Port TROEN: Trace Output Enable bit 1 = Enable Trace Port 0 = Disable Trace Port Reserved: Write `1'; ignore read
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
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27.0 INSTRUCTION SET
The PIC32MX3XX/4XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. PIC32MX does not support the following features: * CoreExtend instructions * Coprocessor 1 instructions * Coprocessor 2 instructions Table 27-1 provides a summary of the instructions that are implemented by the PIC32MX3XX/4XX family core. Note: Refer to "MIPS32(R) Architecture for Programmers Volume II: The MIPS32(R) Instruction Set" at www.mips.com for more information.
TABLE 27-1:
Instruction ADD ADDI ADDIU ADDU AND ANDI B BAL BEQ BEQL
MIPS32(R) INSTRUCTION SET
Description Integer Add Integer Add Immediate Unsigned Integer Add Immediate Unsigned Integer Add Logical AND Logical AND Immediate Unconditional Branch (Assembler idiom for: BEQ r0, r0, offset) Branch and Link (Assembler idiom for: BGEZAL r0, offset) Branch on Equal Branch on Equal Likely(1) Function Rd = Rs + Rt Rt = Rs + Immed Rt = Rs +U Immed Rd = Rs +U Rt Rd = Rs & Rt Rt = Rs & (016 || Immed) PC += (int)offset GPR[31] = PC + 8 PC += (int)offset if Rs == Rt PC += (int)offset if Rs == Rt PC += (int)offset else Ignore Next Instruction if !Rs[31] PC += (int)offset GPR[31] = PC + 8 if !Rs[31] PC += (int)offset GPR[31] = PC + 8 if !Rs[31] PC += (int)offset else Ignore Next Instruction if !Rs[31] PC += (int)offset else Ignore Next Instruction if !Rs[31] && Rs != 0 PC += (int)offset if !Rs[31] && Rs != 0 PC += (int)offset else Ignore Next Instruction if Rs[31] || Rs == 0 PC += (int)offset
BGEZ BGEZAL
Branch on Greater Than or Equal to Zero Branch on Greater Than or Equal to Zero and Link
BGEZALL
Branch on Greater Than or Equal to Zero and Link Likely(1)
BGEZL
Branch on Greater Than or Equal to Zero Likely(1)
BGTZ BGTZL
Branch on Greater Than Zero Branch on Greater Than Zero Likely(1)
BLEZ Note 1:
Branch on Less Than or Equal to Zero This instruction is deprecated and should not be used.
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TABLE 27-1:
Instruction BLEZL
MIPS32(R) INSTRUCTION SET (CONTINUED)
Description Branch on Less Than or Equal to Zero Likely
(1)
Function if Rs[31] || Rs == 0 PC += (int)offset else Ignore Next Instruction if Rs[31] PC += (int)offset GPR[31] = PC + 8 if Rs[31] PC += (int)offset GPR[31] = PC + 8 if Rs[31] PC += (int)offset else Ignore Next Instruction if Rs[31] PC += (int)offset else Ignore Next Instruction if Rs != Rt PC += (int)offset if Rs != Rt PC += (int)offset else Ignore Next Instruction Break Exception Rd = NumLeadingOnes(Rs) Rd = NumLeadingZeroes(Rs) PC = DEPC Exit Debug Mode Rt = Status; StatusIE = 0 LO = (int)Rs / (int)Rt HI = (int)Rs % (int)Rt LO = (uns)Rs / (uns)Rt HI = (uns)Rs % (uns)Rt Stop instruction execution until execution hazards are cleared Rt = Status; StatusIE = 1 if StatusERL PC = ErrorEPC else PC = EPC StatusEXL = 0 StatusERL = 0 LL = 0 Rt = ExtractField(Rs, pos, size) Rt = InsertField(Rs, Rt, pos, size) PC = PC[31:28] || offset<<2
BLTZ BLTZAL
Branch on Less Than Zero Branch on Less Than Zero and Link
BLTZALL
Branch on Less Than Zero and Link Likely(1)
BLTZL
Branch on Less Than Zero Likely(1)
BNE BNEL
Branch on Not Equal Branch on Not Equal Likely(1)
BREAK CLO CLZ DERET DI DIV DIVU EHB
Breakpoint Count Leading Ones Count Leading Zeroes Return from Debug Exception Atomically Disable Interrupts Divide Unsigned Divide Execution Hazard Barrier
EI ERET
Atomically Enable Interrupts Return from Exception
EXT INS J Note 1:
Extract Bit Field Insert Bit Field Unconditional Jump This instruction is deprecated and should not be used.
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TABLE 27-1:
Instruction JAL JALR JALR.HB JR JR.HB LB LBU LH LHU LL Jump and Link Jump and Link Register Jump and Link Register with Hazard Barrier Jump Register Jump Register with Hazard Barrier Load Byte Unsigned Load Byte Load Halfword Unsigned Load Halfword Load Linked Word
MIPS32(R) INSTRUCTION SET (CONTINUED)
Description Function GPR[31] = PC + 8 PC = PC[31:28] || offset<<2 Rd = PC + 8 PC = Rs Like JALR, but also clears execution and instruction hazards PC = Rs Like JR, but also clears execution and instruction hazards Rt = (byte)Mem[Rs+offset] Rt = (ubyte))Mem[Rs+offset] Rt = (half)Mem[Rs+offset] Rt = (uhalf)Mem[Rs+offset] Rt = Mem[Rs+offset> LLbit = 1 LLAdr = Rs + offset Rt = immediate << 16 Rt = Mem[Rs+offset] Rt = Mem[PC+offset] Re = Re MERGE Mem[Rs+offset] Re = Re MERGE Mem[Rs+offset] HI | LO += (int)Rs * (int)Rt HI | LO += (uns)Rs * (uns)Rt Rt = CPR[0, Rd, sel] Rd = HI Rd = LO if Rt 1/4 0 then Rd = Rs if Rt = 0 then Rd = Rs HI | LO -= (int)Rs * (int)Rt HI | LO -= (uns)Rs * (uns)Rt CPR[0, n, Sel] = Rt HI = Rs LO = Rs HI | LO =Unpredictable Rd = ((int)Rs * (int)Rt)31..0 HI | LO = (int)Rs * (int)Rd HI | LO = (uns)Rs * (uns)Rd
LUI LW LWPC LWL LWR MADD MADDU MFC0 MFHI MFLO MOVN MOVZ MSUB MSUBU MTC0 MTHI MTLO MUL MULT MULTU NOP NOR OR ORI RDHWR Note 1:
Load Upper Immediate Load Word Load Word, PC relative Load Word Left Load Word Right Multiply-Add Multiply-Add Unsigned Move from Coprocessor 0 Move from HI Move from LO Move Conditional on Not Zero Move Conditional on Zero Multiply-Subtract Multiply-Subtract Unsigned Move to Coprocessor 0 Move to HI Move to LO Multiply with register write Integer Multiply Unsigned Multiply No Operation (Assembler idiom for: SLL r0, r0, r0) Logical NOR Logical OR Logical OR Immediate Read Hardware Register (if enabled by HWREna Register) This instruction is deprecated and should not be used.
Rd = ~(Rs | Rt) Rd = Rs | Rt Rt = Rs | Immed Re = HWR[Rd]
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TABLE 27-1:
Instruction RDPGPR ROTR ROTRV SB SC Rotate Word Right Rotate Word Right Variable Store Byte Store Conditional Word
MIPS32(R) INSTRUCTION SET (CONTINUED)
Description Read GPR from Previous Shadow Set Function Rt = SGPR[SRSCtlPSS, Rd] Rd = Rtsa-1..0 || Rt31..sa Rd = RtRs-1..0 || Rt31..Rs (byte)Mem[Rs+offset] = Rt if LLbit = 1 mem[Rs+offset> = Rt Rt = LLbit Trap to SW Debug Handler Rd = SignExtend (Rs-7...0) Rd = SignExtend (Rs-15...0) (half)Mem[Rs+offset> = Rt Rd = Rt << sa Rd = Rt << Rs[4:0] if (int)Rs < (int)Rt Rd = 1 else Rd = 0 if (int)Rs < (int)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rt = 1 else Rt = 0 if (uns)Rs < (uns)Immed Rd = 1 else Rd = 0 Rd = (int)Rt >> sa Rd = (int)Rt >> Rs[4:0] Rd = (uns)Rt >> sa Rd = (uns)Rt >> Rs[4:0] NOP Rt = (int)Rs - (int)Rd Rt = (uns)Rs - (uns)Rd Mem[Rs+offset] = Rt Mem[Rs+offset] = Rt Mem[Rs+offset] = Rt Orders the cached coherent and uncached loads and stores for access to the shared memory SystemCallException if Rs == Rt TrapException if Rs == (int)Immed TrapException
SDBBP SEB SEH SH SLL SLLV SLT
Software Debug Break Point Sign-Extend Byte Sign-Extend Half Store Half Shift Left Logical Shift Left Logical Variable Set on Less Than
SLTI
Set on Less Than Immediate
SLTIU
Set on Less Than Immediate Unsigned
SLTU
Set on Less Than Unsigned
SRA SRAV SRL SRLV SSNOP SUB SUBU SW SWL SWR SYNC
Shift Right Arithmetic Shift Right Arithmetic Variable Shift Right Logical Shift Right Logical Variable Superscalar Inhibit No Operation Integer Subtract Unsigned Subtract Store Word Store Word Left Store Word Right Synchronize
SYSCALL TEQ TEQI Note 1:
System Call Trap if Equal Trap if Equal Immediate This instruction is deprecated and should not be used.
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TABLE 27-1:
Instruction TGE TGEI TGEIU TGEU TLT TLTI TLTIU TLTU TNE TNEI WAIT WRPGPR WSBH XOR XORI Note 1:
MIPS32(R) INSTRUCTION SET (CONTINUED)
Description Trap if Greater Than or Equal Trap if Greater Than or Equal Immediate Trap if Greater Than or Equal Immediate Unsigned Trap if Greater Than or Equal Unsigned Trap if Less Than Trap if Less Than Immediate Trap if Less Than Immediate Unsigned Trap if Less Than Unsigned Trap if Not Equal Trap if Not Equal Immediate Wait for Interrupt Write to GPR in Previous Shadow Set Word Swap Bytes Within Halfwords Exclusive OR Exclusive OR Immediate Function if (int)Rs >= (int)Rt TrapException if (int)Rs >= (int)Immed TrapException if (uns)Rs >= (uns)Immed TrapException if (uns)Rs >= (uns)Rt TrapException if (int)Rs < (int)Rt TrapException if (int)Rs < (int)Immed TrapException if (uns)Rs < (uns)Immed TrapException if (uns)Rs < (uns)Rt TrapException if Rs != Rt TrapException if Rs != (int)Immed TrapException Go to a low power mode and stall until interrupt occurs SGPR[SRSCtlPSS, Rd> = Rt Rd = Rt23..16 || Rt31..24 || Rt7..0 || Rt15..8 Rd = Rs ^ Rt Rt = Rs ^ (uns)Immed
This instruction is deprecated and should not be used.
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NOTES:
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PIC32MX3XX/4XX
28.0 DEVELOPMENT SUPPORT
28.1
The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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28.2 MPLAB C Compilers for Various Device Families 28.5 MPLINK Object Linker/ MPLIB Object Librarian
The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
28.3
HI-TECH C for Various Device Families
The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.
28.6
MPLAB Assembler, Linker and Librarian for Various Device Families
28.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
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28.7 MPLAB SIM Software Simulator 28.9
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
MPLAB ICD 3 In-Circuit Debugger System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers.
28.8
MPLAB REAL ICE In-Circuit Emulator System
28.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software.
28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
28.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.
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29.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of PIC32MX3XX/4XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX3XX/4XX are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings (Note 1)
Ambient temperature under bias.............................................................................................................-40C to +105C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V Voltage on VCORE with respect to VSS ....................................................................................................... -0.3V to 2.0V Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2)....................................................................................................200 mA Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2). 3: See the "Pin Diagrams" section for the 5V tolerant pins.
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29.1 DC Characteristics
OPERATING MIPS VS. VOLTAGE
VDD Range (in Volts) 2.3V-3.6V Temp. Range (in C) -40C to +85C Max. Frequency PIC32MX3XX/4XX 80 MHz (Note 1)
TABLE 29-1:
Characteristic DC5 DC5b Note 1:
2.3V-3.6V -40C to +105C 80 MHz (Note 1) 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.
TABLE 29-2:
THERMAL OPERATING CONDITIONS
Rating Symbol TJ TA TJ TA Min. -40 -40 -40 -40 Typical -- -- -- -- Max. +125 +85 +140 +105 Unit C C C C
Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range V-Temp Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - S IOH) I/O Pin Power Dissipation: I/O = S ({VDD - VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation
PD
PINT + PI/O
W
PDMAX
(TJ - TA)/JA
W
TABLE 29-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristics Symbol Typical Max. Unit Notes
JA 40 -- C/W 1 Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm) Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) JA 43 -- C/W 1 Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) JA 47 -- C/W 1 Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) JA 28 -- C/W 1 Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Min. Typical Max. Units Conditions
DC CHARACTERISTICS
Param. Symbol No.
Operating Voltage Supply Voltage DC10 VDD DC12 VDR RAM Data Retention Voltage (Note 1) DC16 VPOR
2.3 1.75
-- --
3.6 --
V V V
-- -- --
VDD Start Voltage 1.75 -- 1.95 to Ensure Internal Power-on Reset Signal DC17 SVDD VDD Rise Rate 0.05 -- -- to Ensure Internal Power-on Reset Signal Note 1: This is the limit to which VDD can be lowered without losing RAM data.
V/ms
--
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TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Max. Units Conditions
DC CHARACTERISTICS
Param. No.
Typical(3)
Operating Current (IDD)(1,2) 8.5 9 DC20c DC21 DC21c DC22 DC22c 4.0 23.5 16.4 48 45 55 60 DC23c DC24 DC24a DC24b DC24c DC25 DC25a DC25b DC25d DC25c DC26 DC26a DC26b DC26c Note 1: 55 -- -- -- -- 94 125 302 400 71 -- -- -- -- 13 15 -- 32 -- 61 -- 75 100 -- 100 130 670 850 -- -- -- -- -- 110 180 700 900 mA A A A A A A A A A A A A A Code executing from SRAM -- -- -- -- -- -- -- -- Code executing from SRAM -- -- -- -- mA mA mA mA mA Code executing from SRAM Code executing from Flash Code executing from SRAM Code executing from Flash Code executing from SRAM -40C, +25C, +85C +105C -- -- -- -40C, +25C, +85C +105C -- -40C +25C +85C +105C -40C +25C +85C +105C -- -40C +25C +85C +105C 3.6V -- 3.3V LPRC (31 kHz) (Note 4) 2.3V -- -- -- 20 MHz (Note 4) 60 MHz (Note 4)
DC20
mA
Code executing from Flash
--
4 MHz
DC23
mA
Code executing from Flash
2.3V
80 MHz
2:
3: 4:
A device's IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type as well as temperature can have an impact on the current consumption. The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by external square wave from rail to rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing.
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TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Max. Units Conditions
DC CHARACTERISTICS
Parameter No.
Typical(2)
Idle Current (IIDLE): Core OFF, Clock ON Base Current (Note 1) DC30 DC30a DC30b DC30c DC31 DC31a DC31b DC31c DC32 DC32a DC32b DC32c DC33 DC33a DC33b DC33c DC34 DC34a DC34b DC34c DC35 DC35a DC35b DC35c DC36 DC36a DC36b DC36c Note 1: -- 1.4 -- -- -- 13 -- -- -- 20 -- -- -- 24 -- -- -- -- -- -- 35 65 242 350 -- -- -- -- 5 -- 5 8 15 -- 17 25 22 -- 25 32 29 -- 32 40 36 62 392 550 -- -- -- -- 43 106 414 600 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A A A A -40C, +25C, +85C -40C, +25C, +85C -40C, +25C, +85C +105C -40C, +25C, +85C -40C, +25C, +85C -40C, +25C, +85C +105C -40C, +25C, +85C -40C, +25C, +85C -40C, +25C, +85C +105C -40C, +25C, +85C -40C, +25C, +85C -40C, +25C, +85C +105C -40C +25C +85C +105C -40C +25C +85C +105C -40C +25C +85C +105C 3.6V 3.3V LPRC (31 kHz) (Note 3) 2.3V 2.3V -- 3.6V 2.3V -- 3.6V 2.3V -- 3.6V 2.3V -- 3.6V 80 MHz 60 MHz (Note 3) 20 MHz (Note 3) 4 MHz
2: 3:
The test conditions for base IDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:8. CPU in Idle mode (CPU core halted). Only digital peripheral modules are enabled (ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing.
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TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Max. Units Conditions
DC CHARACTERISTICS Parameter Typical(2) No. DC40 DC40a DC40b DC40h DC40c DC40d DC40e DC40g DC40f DC40i DC41 DC41a DC41b DC41g DC41c DC41d DC41e DC41f DC41h DC42 DC42a DC42b DC42h DC42c DC42e DC42f DC42g DC42i Note 1: 2: 3: 4: 5: 6: 7 24 205 450 25 9 25 115 200 470 -- -- -- -- 5 -- -- -- -- -- -- -- -- 23 -- -- -- --
Power-Down Current (IPD)(1) 30 30 300 900 -- 70 70 200(5) 400 1200 10 10 10 12 -- 10 10 12 15 10 17 37 45 -- 10 30 44 44 A A A A A A A A A A A A A A A A A A A A A A A A A A A A -40C +25C +85C +105C +25C -40C +25C +70C +85C +105C -40C +25C +85C +105C +25C -40C +25C +85C +105C -40C +25C +85C +105C +25C -40C +25C +85C +105C 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3) 2.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3, 6) 3.6V Watchdog Timer Current: IWDT (Note 3) 3.3V Watchdog Timer Current: IWDT (Note 3) 2.3V Watchdog Timer Current: IWDT (Notes 3, 6) 3.6V Base Power-Down Current 3.3V Base Power-Down Current 2.3V Base Power-Down Current (Note 6)
Module Differential Current
Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing.
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TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Max. Units Conditions DC CHARACTERISTICS Parameter Typical(2) No. DC43 DC43a DC43b DC43h DC43c DC43e DC43f DC43g DC43i Note 1: 2: 3: 4: 5: 6: -- -- -- -- 880 -- -- -- --
Module Differential Current (Continued) 1100 1100 1000 1200 -- 1100 1100 1000 1200 A A A A A A A A A -40C +25C +85C +105C -- -40C +25C +85C +105C 3.6V ADC: IADC (Notes 3, 4) -- ADC: IADC (Notes 3, 4) 2.5V ADC: IADC (Notes 3, 4, 6)
Base IPD is measured with all digital peripheral modules disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. Data in the "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. Data is characterized at +70C and not tested. Parameter is for design guidance only. This parameter is characterized, but not tested in manufacturing.
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TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical(1) Max. Units Conditions
DC CHARACTERISTICS
Param. Symbol No. VIL DI10
Characteristics Input Low Voltage I/O pins: with TTL Buffer with Schmitt Trigger Buffer
VSS VSS VSS VSS VSS VSS VSS
-- -- -- -- -- -- --
0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8
V V V V V V V
(Note 4) (Note 4) (Note 4) (Note 4) (Note 4) SMBus disabled (Note 4) SMBus enabled (Note 4)
DI15 DI16 DI17 DI18 DI19 VIH DI20
MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx Input High Voltage I/O pins: with Analog Functions Digital Only with TTL Buffer with Schmitt Trigger Buffer
0.8 VDD 0.8 VDD 0.25VDD + 0.8V 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1
-- -- -- -- -- -- -- -- --
VDD 5.5 5.5 VDD VDD VDD 5.5 5.5
V V V V V V V V V
(Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) SMBus disabled (Note 4) SMBus enabled, 2.3V VPIN 5.5 (Note 4) VDD = 3.3V, VPIN = VSS (Note 3) VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VSS VPIN VDD, XT and HS modes
DI25 DI26 DI27 DI28 DI29
MCLR OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx SDAx, SCLx
DI30 DI50 DI51 DI55 DI56 Note 1: 2:
ICNPU IIL
CNxx Pull up Current Input Leakage Current I/O Ports Analog Input Pins MCLR OSC1
50 -- -- -- --
250 -- -- -- --
400 +1 +1 +1 +1
A A A A A
3: 4:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing.
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TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions
DC CHARACTERISTICS
Param. Symbol No. VOL DO10 DO16 VOH DO20 DO26
Characteristics Output Low Voltage I/O Ports OSC2/CLKO Output High Voltage I/O Ports OSC2/CLKO
-- -- -- -- 2.4 1.4 2.4 1.4
-- -- -- -- -- -- -- --
0.4 0.4 0.4 0.4 -- -- -- --
V V V V V V V V
IOL = 7 mA, VDD = 3.6V IOL = 6 mA, VDD = 2.3V IOL = 3.5 mA, VDD = 3.6V IOL = 2.5 mA, VDD = 2.3V IOH = -12 mA, VDD = 3.6V IOH = -12 mA, VDD = 2.3V IOH = -12 mA, VDD = 3.6V IOH = -12 mA, VDD = 2.3V
TABLE 29-10: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. 2.0 Typical -- Max. 2.3 Units V Conditions --
Param. Symbol No. BO10 VBOR
Characteristics BOR Event on VDD transition high-to-low
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TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY(3)
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Program Flash Memory D130 D131 D132 D134 D135 EP VPR VPEW TRETD IDDP TWW D136 D137 D138 Note 1: 2: TRW TPE TCE Cell Endurance VDD for Read VDD for Erase or Write Characteristic Retention Supply Current during Programming Word Write Cycle Time Row Write Cycle Time (128 words per row)
(2)
Param. No.
Symbol
Min.
Typical(1) Max. Units
Conditions
1000 VMIN 3.0 20 -- 20 3 20 80 --
-- -- -- -- 10 -- 4.5 -- -- --
-- 3.6 3.6 -- -- 40 -- -- -- 6
E/W V V Year mA s ms ms ms s
-- -- -- -- -- -- -- -- -- --
Page Erase Cycle Time Chip Erase Cycle Time
LVDstartup Flash LVD Delay
3:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to the "PIC32MX Flash Programming Specification" (DS61145) for operating conditions during programming and erase cycles.
TABLE 29-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp SYSCLK 0 to 30 31 to 60 61 to 80 MHz -- Units Comments
Required Flash wait states 0 Wait State 1 Wait State 2 Wait States Note 1:
40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices.
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TABLE 29-13: COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Input Offset Voltage Min. -- Typical 7.5 Max. 25 Units mV Comments
Param. Symbol No. D300 D301 VIOFF
D302 D303
D304
D305 Note
AVDD = VDD, AVSS = VSS VICM Input Common Mode Voltage 0 -- VDD V AVDD = VDD, AVSS = VSS (Note 2) CMRR Common Mode Rejection Ratio 55 -- -- dB Max VICM = (VDD - 1)V (Note 2) Response Time -- 150 400 ns AVDD = VDD, TRESP AVSS = VSS (Notes 1,2) ON2OV Comparator Enabled to Output -- -- 10 s Comparator module is Valid configured before setting the comparator ON bit. (Note 2) Internal Voltage Reference 0.57 0.6 0.63 V -- IVREF 1: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. 2: These parameters are characterized but not tested.
TABLE 29-14: VOLTAGE REFERENCE SPECIFICATIONS
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Resolution Absolute Accuracy Settling Time(1) Min. VDD/24 -- -- Typical -- -- -- Max. VDD/32 1/2 10 Units LSb LSb s Comments -- -- --
Param. No. D310 D311 D312 Note 1:
Symbol VRES VRAA TSET
Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'. This parameter is characterized, but not tested in manufacturing.
TABLE 29-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
DC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Regulator Output Voltage External Filter Capacitor Value Power-up Timer Period Min. 1.62 8 -- Typical 1.80 10 64 Max. 1.98 -- -- Units V F ms Comments -- Capacitor must be low series resistance (< 1 Ohm) ENVREG = 0
Param. No. D320 D321 D322
Symbol VCORE CEFC TPWRT
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(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
29.2 AC Characteristics and Timing Parameters
The information contained in this section defines PIC32MX3XX/4XX AC characteristics and timing parameters.
FIGURE 29-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 - for OSC2
Load Condition 1 - for all pins except OSC2 VDD/2
RL
Pin VSS
CL
Pin VSS
CL
RL = 464 CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode)
TABLE 29-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. -- -- Typical(1) -- -- Max. 50 400 Units pF pF EC mode In I2CTM mode Conditions
Param. Symbol No. DO56 DO58 Note 1: CIO CB
Characteristics All I/O pins and OSC2 SCLx, SDAx
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
FIGURE 29-2:
EXTERNAL CLOCK TIMING
OS20 OS30 OS31
OSC1
OS30 OS31
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TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency Min. DC 4 3 4 10 10 32 TOSC TOSC = 1/FOSC = TCY(2) -- Typical(1) -- -- -- -- -- -- 32.768 -- Max. 50(3) 50(5) 10 10 25 25 100 -- Units MHz MHz MHz MHz MHz MHz kHz -- Conditions EC (Note 5) ECPLL (Note 4) XT (Note 5) XTPLL (Notes 4, 5) HS (Note 5) HSPLL (Notes 4, 5) SOSC (Note 5) See parameter OS10 for FOSC value EC (Note 5) EC (Note 5) (Note 5)
Param. Symbol No. OS10 FOSC
OS11 OS12 OS13 OS14 OS15 OS20
OS30 OS31 OS40
TOSL, TOSH TOSR, TOSF TOST
External Clock In (OSC1) High or Low Time External Clock In (OSC1) Rise or Fall Time Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) Primary Clock Fail Safe Time-out Period External Oscillator Transconductance
0.45 x TOSC -- --
-- -- 1024
-- 0.05 x TOSC --
ns ns TOSC
OS41 OS42
TFSCM GM
-- --
2 12
-- --
ms
(Note 5)
mA/V VDD = 3.3V TA = +25C (Note 5)
Note 1: 2:
3: 4: 5:
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. 40 MHz maximum for PIC32MX320F032H and PIC32MX420F032H devices. PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing.
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TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Period Jitter or Cumulative)
(2)
Param. Symbol No. OS50 FPLLI
Min. 4
Typical --
Max. 5
Units MHz
Conditions ECPLL, HSPLL, XTPLL, FRCPLL modes -- -- Measured over 100 ms period
OS51 OS52 OS53 Note 1: 2:
FSYS TLOCK DCLK
60 -- -0.25
-- -- --
120 2 +0.25
MHz ms %
These parameters are characterized, but not tested in manufacturing. This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D CLK EffectiveJitter = -------------------------------------------------------------SYSCLK --------------------------------------------------------CommunicationClock For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: D CLK D CLK EffectiveJitter = ------------- = ------------2 80 ----20
TABLE 29-19:
INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions
AC CHARACTERISTICS
Param. No.
Characteristics
Internal FRC Accuracy @ 8.00 MHz(1) F20 Note 1: FRC -2 -- +2 % -- Frequency calibrated at 25C and 3.3V. TUN bits can be used to compensate for temperature drift.
TABLE 29-20: INTERNAL RC ACCURACY
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions
Param. No.
Characteristics
LPRC @ 31.25 kHz(1) F21 Note 1: LPRC -15 -- +15 % -- Change of LPRC frequency as VDD changes.
(c) 2011 Microchip Technology Inc.
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FIGURE 29-3:
I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 29-1 for load conditions. DO31 DO32
I/O TIMING CHARACTERISTICS
TABLE 29-21: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(2) Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time CNx High or Low Time (input) Min. -- -- DO32 DI35 DI40 Note 1: 2: TIOF TINP TRBP -- -- 10 2 Typical(1) 5 5 5 5 -- -- Max. 15 10 15 10 -- -- Units ns ns ns ns ns TSYSCLK Conditions VDD < 2.5V VDD > 2.5V VDD < 2.5V VDD > 2.5V -- --
Param. No. DO31
Symbol TIOR
Data in "Typical" column is at 3.3V, 25C unless otherwise stated. This parameter is characterized, but not tested in manufacturing.
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FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY) SY02
Power Up Sequence (Note 2) SY00 (TPU) (Note 1) CPU starts fetching code
Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR (TSYSDLY) SY02
Power Up Sequence (Note 2) SY00 (TPU) (Note 1) SY10 (TOST) CPU starts fetching code
External VCORE Provided Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD VCORE
VPOR
(TSYSDLY) SY02 Power Up Sequence (Note 3) SY01 (TPWRT) (Note 1) CPU starts fetching code
Note 1: The Power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay. 3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
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FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR (SY20) BOR
TBOR (SY30) Reset Sequence
(TSYSDLY) SY02
CPU starts fetching code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
Reset Sequence
(TSYSDLY) SY02
TOST (SY10)
CPU starts fetching code
TABLE 29-22: RESETS TIMING
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) Power-up Period Internal Voltage Regulator Enabled Power-up Period External Vcore Applied (Power-Up-Timer Active) Min. -- 48 Typical(2) 400 64 Max. 600 80 Units s ms Conditions -40C to +85C -40C to +85C
Param. Symbol No. SY00 SY01 TPU TPWRT
SY02
TSYSDLY System Delay Period: Time required to reload Device Configuration Fuses plus SYSCLK delay before first instruction is fetched. TMCLR TBOR MCLR Pulse Width (low) BOR Pulse Width (low)
--
1 s + 8 SYSCLK cycles
--
--
-40C to +85C
SY20 SY30 Note 1: 2:
-- --
2 1
-- --
s s
-40C to +85C -40C to +85C
These parameters are characterized, but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Characterized by design but not tested.
DS61143H-page 166
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK Tx10 Tx11
Tx15 OS60 TMRx
Tx20
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(2) TxCK High Time Synchronous, with prescaler Asynchronous, with prescaler TA11 TTXL TxCK Low Time Synchronous, with prescaler Asynchronous, with prescaler TA15 TTXP TxCK Synchronous, Input Period with prescaler Min. [(12.5 ns or 1TPB)/N] + 25 ns 10 [(12.5 ns or 1TPB)/N] + 25 ns 10 [(Greater of 25 ns or 2TPB)/N] + 30 ns [(Greater of 25 ns or 2TPB)/N] + 50 ns Asynchronous, with prescaler 20 50 OS60 FT1 SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON<1>)) 32 Typical Max. Units -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 ns ns ns ns ns ns ns ns kHz Conditions Must also meet parameter TA15. -- Must also meet parameter TA15. -- VDD > 2.7V VDD < 2.7V VDD > 2.7V (Note 3) VDD < 2.7V (Note 3) --
Param. No. TA10
Symbol TTXH
TA20
TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment
--
1
TPB
--
Note 1: 2: 3:
Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. N = prescale value (1, 8, 64, 256)
(c) 2011 Microchip Technology Inc.
DS61143H-page 167
PIC32MX3XX/4XX
TABLE 29-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. [(12.5 ns or 1TPB)/N] + 25 ns [(12.5 ns or 1TPB)/N] + 25 ns [(Greater of 25 ns or 2 TPB)/N] + 30 ns [(Greater of 25 ns or 2 TPB)/N] + 50 ns -- Max. Units -- ns Conditions Must also meet N = prescale value parameter (1, 2, 4, 8, 16, TB15. Must also meet 32, 64, 256) parameter TB15. -- -- 1 ns ns TPB VDD > 2.7V VDD < 2.7V -- --
Param. No. TB10
Symbol TTXH
Characteristics(1) TxCK High Time TxCK Low Time TxCK Input Period Synchronous, with prescaler Synchronous, with prescaler Synchronous, with prescaler
TB11
TTXL
--
ns
TB15
TTXP
TB20
TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS61143H-page 168
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 29-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10 IC15
IC11
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. [(12.5 ns or 1TPB)/N] + 25 ns Max. -- Units ns Conditions Must also meet parameter IC15. Must also meet parameter IC15. -- N = prescale value (1, 4, 16)
Param. Symbol No. IC10 TCCL
Characteristics(1) ICx Input Low Time
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1TPB)/N] + 25 ns
--
ns
IC15 Note 1:
TCCP
ICx Input Period
[(25 ns or 2TPB)/N] + 50 ns
--
ns
These parameters are characterized, but not tested in manufacturing.
FIGURE 29-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx (Output Compare or PWM Mode)
OC11
OC10
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. -- -- Typical(2) -- -- Max. -- -- Units ns ns Conditions See parameter DO32. See parameter DO31.
Param. Symbol No. OC10 OC11 Note 1: 2: TCCF TCCR
Characteristics(1) OCx Output Fall Time OCx Output Rise Time
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
(c) 2011 Microchip Technology Inc.
DS61143H-page 169
PIC32MX3XX/4XX
FIGURE 29-9: OC/PWM MODULE TIMING CHARACTERISTICS
OC20 OCFA/OCFB
OC15
OCx
OCx is tri-stated
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) Fault Input to PWM I/O Change Fault Input Pulse Width Min -- 50 Typical(2) -- -- Max 25 -- Units ns ns Conditions -- --
Param No. OC15 OC20 Note 1: 2:
Symbol TFD TFLT
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested.
DS61143H-page 170
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 29-10:
SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 SP21 SP10
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SP21
SP20
SDOx SP31 SDIx
MSb
Bit 14 - - - - - -1 SP30 Bit 14 - - - -1
LSb
MSb In SP40 SP41
LSb In
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) SCKx Output Low Time(3) SCKx Output High SCKx Output Fall Time(3) Time(4) Min. TSCK/2 TSCK/2 -- -- -- -- -- -- 10 10 Typical(2) Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 20 -- -- Units ns ns ns ns ns ns ns ns ns ns Conditions -- -- See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V -- --
Param. No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4:
Symbol TSCL TSCH TSCF TSCR TDOF TDOR
SCKx Output Rise Time(4) SDOx Data Output Fall Time(4) SDOx Data Output Rise Time(4)
TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins.
(c) 2011 Microchip Technology Inc.
DS61143H-page 171
PIC32MX3XX/4XX
FIGURE 29-11:
SCKX (CKP = 0) SP11 SP10 SP21 SP20
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX (CKP = 1) SP35 SP20 SP21
SDOX
MSb
Bit 14 - - - - - -1 SP30,SP31
LSb
SDIX SP40
MSb In SP41
Bit 14 - - - -1
LSb In
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) SCKx Output Low Time(3) SCKx Output High Time(3) SCKx Output Fall Time(4) Time(4) SCKx Output Rise Min. TSCK/2 TSCK/2 -- -- -- -- -- -- 15 15 20 15 20 Typical(2) -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- 15 20 -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions -- -- See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V -- VDD > 2.7V VDD < 2.7V VDD > 2.7V VDD < 2.7V
Param. No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4:
Symbol TSCL TSCH TSCF TSCR TDOF TDOR
SDOx Data Output Fall Time(4) SDOx Data Output Rise Time(4)
TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge
These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins.
DS61143H-page 172
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 29-12:
SSX SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 Bit 14 - - - - - -1 SP30,SP31 SDIX SP40 MSb In SP41 Bit 14 - - - -1 LSb In SP73 LSb SP51 SP70 SP73 SP72 SP52
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) SCKx Input Low Time(3) SCKx Input High Time(3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time(4) SDOx Data Output Rise Time(4) Min. TSCK/2 TSCK/2 -- -- -- -- -- -- 10 10 175 5 Typical(2) -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- 15 20 -- -- -- 25 Units ns ns ns ns ns ns ns ns ns ns ns ns Conditions -- -- See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V -- -- -- --
Param. No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 Note 1: 2: 3: 4:
Symbol TSCL TSCH TSCF TSCR TDOF TDOR
TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge
TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL TSSH2DOZ SSx to SDOx Output High-Impedance(3)
TSCH2SSH SSx after SCKx Edge TSCK + 20 -- -- ns -- TSCL2SSH These parameters are characterized, but not tested in manufacturing. Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 40 ns. Assumes 50 pF load on all SPIx pins.
(c) 2011 Microchip Technology Inc.
DS61143H-page 173
PIC32MX3XX/4XX
FIGURE 29-13:
SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP72 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI SP40 MSb In SP41 Bit 14 - - - -1 LSb In LSb SP51 SP73 SP70 SP73 SP72 SP52
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
Note: Refer to Figure 29-1 for load conditions.
TABLE 29-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) Min. TSCK/2 TSCK/2 -- -- -- -- -- -- Typical(2) -- -- 5 5 -- -- -- -- Max. -- -- 10 10 -- -- 20 30 -- Units ns ns ns ns ns ns ns ns Conditions -- -- -- -- See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V --
Param. No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 SP60 Note
Symbol TSCL TSCH TSCF TSCR
SCKx Input Low Time(3) SCKx Input High Time(3) SCKx Input Fall Time SCKx Input Rise Time TDOF SDOx Data Output Fall Time(4) TDOR SDOx Data Output Rise Time(4) TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL
Setup Time of SDIx Data Input -- ns 10 to SCKx Edge Hold Time of SDIx Data Input -- -- ns -- 10 to SCKx Edge 175 -- -- ns -- TSSL2SCH, SSx to SCKx or SCKx TSSL2SCL Input TSSH2DOZ SSx to SDOX Output 5 -- 25 ns -- High-Impedance(4) TSCK + -- -- ns -- TSCH2SSH SSx after SCKx Edge TSCL2SSH 20 TSSL2DOV SDOx Data Output Valid after -- -- ns -- 25 SSx Edge 1: These parameters are characterized, but not tested in manufacturing. 2: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCKx is 40 ns. 4: Assumes 50 pF load on all SPIx pins.
DS61143H-page 174
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM30 IM33 IM34
SDAx
Start Condition Note: Refer to Figure 29-1 for load conditions.
Stop Condition
FIGURE 29-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM10 IM11 IM26 IM21
SCLx
IM10
IM25
IM33
SDAx In
IM40 IM40 IM45
SDAx Out
Note: Refer to Figure 29-1 for load conditions.
(c) 2011 Microchip Technology Inc.
DS61143H-page 175
PIC32MX3XX/4XX
TABLE 29-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Min.(1) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) -- 20 + 0.1 CB -- -- 20 + 0.1 CB -- 250 100 100 0 0 0 TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) -- -- -- 4.7 1.3 0.5 Max. -- -- -- -- -- -- 300 300 100 1000 300 300 -- -- -- -- 0.9 0.3 -- -- -- -- -- -- -- -- -- -- -- -- 3500 1000 350 -- -- -- Units s s s s s s ns ns ns ns ns ns ns ns ns s s s s s s s s s s s s ns ns ns ns ns ns s s s -- The amount of time the bus must be free before a new transmission can start. -- -- -- -- CB is specified to be from 10 to 400 pF. CB is specified to be from 10 to 400 pF. -- Conditions
Param. Symbol No. IM10
TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode
(2)
--
IM11
THI:SCL
Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(2)
IM20
TF:SCL
IM21
IM25
IM26
IM30
SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(2) 100 kHz mode TSU:DAT Data Input Setup Time 400 kHz mode 1 MHz mode(2) 100 kHz mode THD:DAT Data Input Hold Time 400 kHz mode 1 MHz mode(2) TSU:STA Start Condition 100 kHz mode Setup Time 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode
(2)
--
-- Only relevant for Repeated Start condition. After this period, the first clock pulse is generated.
IM31
THD:STA Start Condition Hold Time
IM33
TSU:STO Stop Condition Setup Time
IM34
THD:STO Stop Condition Hold Time
100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2) 100 kHz mode 400 kHz mode 1 MHz mode(2)
IM40
TAA:SCL
Output Valid from Clock
IM45
TBF:SDA Bus Free Time
Bus Capacitive Loading -- 400 pF IM50 CB Pulse Gobbler Delay(3) 52 312 ns IM51 TPGD Note 1: BRG is the value of the I2CTM Baud Rate Generator. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: The typical value for this parameter is 104 ns.
DS61143H-page 176
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS30 IS33 IS34
SDAx
Start Condition Note: Refer to Figure 29-1 for load conditions.
Stop Condition
FIGURE 29-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS10 IS30 IS26 IS21
SCLx
IS31
IS25
IS33
SDAx In
IS40 IS40 IS45
SDAx Out
Note: Refer to Figure 29-1 for load conditions.
(c) 2011 Microchip Technology Inc.
DS61143H-page 177
PIC32MX3XX/4XX
TABLE 29-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode Min. 4.7 1.3 0.5 4.0 0.6 Max. -- -- -- -- -- Units s s s s s Conditions PBCLK must operate at a minimum of 800 KHz. PBCLK must operate at a minimum of 3.2 MHz. -- PBCLK must operate at a minimum of 800 KHz. PBCLK must operate at a minimum of 3.2 MHz. -- CB is specified to be from 10 to 400 pF. CB is specified to be from 10 to 400 pF.
Param. No. IS10
Symbol TLO:SCL
IS11
THI:SCL
Clock High Time
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50 Note
0.5 -- s 1 MHz mode(1) SDAx and SCLx 100 kHz mode -- 300 ns TF:SCL Fall Time 300 ns 400 kHz mode 20 + 0.1 CB 1 MHz mode(1) -- 100 ns SDAx and SCLx 100 kHz mode -- 1000 ns TR:SCL Rise Time 300 ns 400 kHz mode 20 + 0.1 CB 1 MHz mode(1) -- 300 ns 100 kHz mode 250 -- ns TSU:DAT Data Input Setup Time 400 kHz mode 100 -- ns 100 -- ns 1 MHz mode(1) 100 kHz mode 0 -- ns THD:DAT Data Input Hold Time 400 kHz mode 0 0.9 s 0 0.3 s 1 MHz mode(1) 100 kHz mode 4700 -- ns TSU:STA Start Condition Setup Time 400 kHz mode 600 -- ns 250 -- ns 1 MHz mode(1) 100 kHz mode 4000 -- ns THD:STA Start Condition Hold Time 400 kHz mode 600 -- ns 250 -- ns 1 MHz mode(1) 100 kHz mode 4000 -- ns TSU:STO Stop Condition Setup Time 400 kHz mode 600 -- ns 600 -- ns 1 MHz mode(1) 100 kHz mode 4000 -- ns THD:STO Stop Condition Hold Time 400 kHz mode 600 -- ns 250 ns 1 MHz mode(1) 0 3500 ns TAA:SCL Output Valid from 100 kHz mode Clock 400 kHz mode 0 1000 ns 0 350 ns 1 MHz mode(1) 100 kHz mode 4.7 -- s TBF:SDA Bus Free Time 400 kHz mode 1.3 -- s (1) 0.5 -- s 1 MHz mode CB Bus Capacitive Loading -- 400 pF 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
--
-- Only relevant for Repeated Start condition. After this period, the first clock pulse is generated.
--
--
-- The amount of time the bus must be free before a new transmission can start. --
DS61143H-page 178
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PIC32MX3XX/4XX
TABLE 29-34: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions
Param. No.
Symbol
Characteristics
Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 2.5 VSS AVSS + 2.0 2.5 VREFL VREF Reference Voltage Low Absolute Reference Voltage (VREFH - VREFL) Current Drain AVSS 2.0 -- Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 VREFH - 2.0 AVDD V -- V V V V V (Note 1) VREFH = AVDD (Note 3) (Note 1) (Note 3) --
AD02 AD05 AD05a AD06 AD07
AVSS VREFH
Module VSS Supply Reference Voltage High
-- -- -- -- --
Reference Inputs
AD08
IREF
--
250 -- -- -- -- 0.001
400 3 VREFH AVDD/2 AVDD + 0.3 0.610
A A V V V A
ADC operating ADC off -- -- -- VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10K (Note 1)
Analog Input AD12 AD13 AD14 AD15 VINH-VINL Full-Scale Input Span VINL VIN -- Absolute VINL Input Voltage Absolute Input Voltage Leakage Current VREFL AVSS - 0.3 AVSS - 0.3 --
AD17
RIN
Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity
--
--
5K
ADC Accuracy - Measurements with External VREF+/VREFAD20c Nr AD21c INL AD22c DNL 10 data bits -- -- -- -- <1 <1 bits -- LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V (Note 2) LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V LSb VINL = AVSS = 0V, AVDD = 3.3V -- Guaranteed
AD23c GERR AD24n EOFF AD25c Note 1: 2: 3: 4: --
Gain Error Offset Error Monotonicity
-- -- --
-- -- --
<1 <1 --
These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with 1 kHz sinewave.
(c) 2011 Microchip Technology Inc.
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PIC32MX3XX/4XX
TABLE 29-34: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Min. Typical Max. Units Conditions
Param. No.
Symbol
Characteristics
ADC Accuracy - Measurements with Internal VREF+/VREFAD20d Nr AD21d INL Resolution Integral Nonlinearity -- 10 data bits -- <1 bits (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Notes 2,3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.6V (Note 3) -- dB bits Guaranteed (Notes 3, 4) (Notes 3, 4)
AD22d DNL
Differential Nonlinearity
--
--
<1
AD23d GERR
Gain Error
--
--
<4
AD24d EOFF
Offset Error
--
--
<2
AD25d AD31b AD34b Note 1: 2: 3: 4:
-- SINAD ENOB
Monotonicity Signal to Noise and Distortion Effective Number of Bits
-- 55 9.0
-- 58.5 9.5
-- -- --
Dynamic Performance
These parameters are not characterized or tested in manufacturing. With no missing codes. These parameters are characterized, but not tested in manufacturing. Characterized with 1 kHz sinewave.
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PIC32MX3XX/4XX
TABLE 29-35: 10-BIT ADC CONVERSION RATE PARAMETERS(2)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp ADC Speed 1 MIPS to 400 ksps(1) Sampling TAD RS Max Minimum Time Min 65 ns 132 ns 500 VDD 3.0V to 3.6V
VREF- VREF+
ADC Channels Configuration
ANx
CHX SHA ADC
Up to 400 ksps
200 ns
200 ns
5.0 k 2.5V to 3.6V
VREF- VREF+ or or AVSS AVDD
ANx
CHX SHA ADC
ANx or VREF-
Up to 300 ksps
200 ns
200 ns
5.0 k 2.5V to 3.6V
VREF- VREF+ or or AVSS AVDD
ANx
CHX SHA ADC
ANx or VREF-
Note 1: 2:
External VREF- and VREF+ pins must be used for correct operation. These parameters are characterized, but not tested in manufacturing.
(c) 2011 Microchip Technology Inc.
DS61143H-page 181
PIC32MX3XX/4XX
TABLE 29-36: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics Min. Typical(1) Max. Units Conditions
Param. Symbol No. Clock Parameters AD50 AD51 TAD
TRC
Analog-to-Digital Clock Period Analog-to-Digital Internal RC Oscillator Period Conversion Time Throughput Rate (Sampling Speed) Sample Time
65 --
-- 250
-- --
ns ns
See Table 29-35 and Note 2 See Note 3
Conversion Rate AD55 AD56 AD57
TCONV
-- -- -- 1 TAD
12 TAD -- -- --
-- 1000 400 --
-- KSPS KSPS --
-- AVDD = 3.0V to 3.6V AVDD = 2.5V to 3.6V TSAMP must be 132 ns. Auto-Convert Trigger (SSRC<2:0> = 111) not selected. See Note 3 -- See Note 3 See Note 3
FCNV TSAMP
Timing Parameters AD60
TPCS
Conversion Start from Sample Trigger
--
1.0 TAD
--
--
AD61 AD62 AD63
TPSS
Sample Start from Setting Sample (SAMP) bit Conversion Completion to Sample Start (ASAM = 1) Time to Stabilize Analog Stage from Analog-to-Digital OFF to Analog-to-Digital ON
0.5 TAD -- --
-- 0.5 TAD --
1.5 TAD -- 2
-- -- s
TCSS
TDPU
Note 1: 2: 3:
These parameters are characterized, but not tested in manufacturing. Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Characterized by design but not tested.
DS61143H-page 182
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FIGURE 29-18: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50 ADCLK Instruction Execution Set SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 TSAMP CONV ADxIF Buffer(0) Buffer(1) AD55 AD55 Clear SAMP
1
2
3
4
5
6
7
8
5
6
7
8
1 - Software sets ADxCON. SAMP to start sampling. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS61104) of the "PIC32 Family Reference Manual". 3 - Software clears ADxCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 7 - Convert bit 0. 8 - One TAD for end of conversion.
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FIGURE 29-19: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction Execution SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc
Set ADON
TSAMP
AD55 CONV ADxIF Buffer(0) Buffer(1) AD55
TSAMP TCONV
1
2
3
4
5
6
7
3
4
5
6
8
3
4
1 - Software sets ADxCON. ADON to start AD operation. 2 - Sampling starts after discharge period. TSAMP is described in Section 17. "10-bit Analog-to-Digital Converter (ADC)" (DS61104) of the "PIC32 Family Reference Manual". 3 - Convert bit 9. 4 - Convert bit 8. 5 - Convert bit 0. 6 - One TAD for end of conversion. 7 - Begin conversion of next channel. 8 - Sample for time specified by SAMC<4:0>.
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FIGURE 29-20:
CS
PARALLEL SLAVE PORT TIMING
PS5 RD
PS6 WR
PS4
PS7
PMD<7:0> PS1 PS2
PS3
TABLE 29-37: PARALLEL SLAVE PORT REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) Min. 20 40 -- 0 TPB + 40 TPB + 25 TPB + 25 Typical -- -- -- -- -- -- -- Max. -- -- 60 10 -- -- -- Units ns ns ns ns ns ns ns Conditions -- -- -- -- -- -- --
Param. No. PS1 PS2 PS3 PS4 PS5 PS6 PS7 Note 1:
Symbol
TdtV2wrH Data In Valid before WR or CS Inactive (setup time) TwrH2dtI TrdL2dtV TrdH2dtI Tcs TWR TRD WR or CS Inactive to Data - In Invalid (hold time) RD and CS Active to Data - Out Valid RD Active or CS Inactive to Data - Out Invalid CS Active Time WR Active Time RD Active Time
These parameters are characterized, but not tested in manufacturing.
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FIGURE 29-21: PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PM4 PMA<13:18> Address PM6 PMD<7:0> Address<7:0> Address<7:0> PM2 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PM7 Data Data
PMCS<2:1>
TABLE 29-38: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) PMALL/PMALH Pulse Width Address Out Valid to PMALL/PMALH Invalid (address setup time) Min. -- -- -- 5 Typical 1 TPB 2 TPB 1 TPB -- Max. -- -- -- -- Units -- -- -- ns Conditions -- -- -- --
Param. Symbol No. PM1 PM2 PM3 PM4 TLAT TADSU
TADHOLD PMALL/PMALH Invalid to Address Out Invalid (address hold time) TAHOLD PMRD Inactive to Address Out Invalid (address hold time) PMRD Pulse Width PMRD or PMENB Active to Data In Valid (data setup time) PMRD or PMENB Inactive to Data In Invalid (data hold time)
PM5 PM6 PM7 Note 1:
TRD TDSU TDHOLD
-- 15 --
1 TPB -- 80
-- -- --
-- ns ns
-- -- --
These parameters are characterized, but not tested in manufacturing.
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PIC32MX3XX/4XX
FIGURE 29-22: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB TPB TPB TPB TPB TPB TPB TPB
PB Clock
PMA<13:18> PM2 + PM3 PMD<7:0> Address<7:0>
Address
Data PM12
PM13 PM11
PMRD
PMWR PM1 PMALL/PMALH
PMCS<2:1>
TABLE 29-39: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) PMWR Pulse Width Data Out Valid before PMWR or PMENB goes Inactive (data setup time) Min. -- -- Typical 1 TPB 2 TPB Max. -- -- Units -- -- Conditions -- --
Param. Symbol No. PM11 PM12 TWR TDVSU
PM13 Note 1:
TDVHOLD PMWR or PMEMB Invalid to Data Out Invalid (data hold time)
--
1 TPB
--
--
--
These parameters are characterized, but not tested in manufacturing.
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TABLE 29-40: OTG ELECTRICAL SPECIFICATIONS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Characteristics(1) USB Voltage Min. 3.0 Typ -- Max. 3.6 Units V Conditions Voltage on VUSB must be in this range for proper USB operation. -- -- The difference between D+ and Dmust exceed this value while VCM is met. -- -- 1.5 k load connected to 3.6V. 1.5 k load connected to ground.
Param. Symbol No. USB313 VUSB
USB315 VILUSB USB316 VIHUSB USB318 VDIFS
Input Low Voltage for USB Buffer Input High Voltage for USB Buffer Differential Input Sensitivity
-- 2.0 --
-- -- --
0.8 -- 0.2
V V V
USB319 VCM USB320 ZOUT USB321 VOL USB322 VOH Note 1:
Differential Common Mode Range Driver Output Impedance Voltage Output Low Voltage Output High
0.8 28.0 0.0 2.8
-- -- -- --
2.5 44.0 0.3 3.6
V V V
These parameters are characterized, but not tested in manufacturing.
DS61143H-page 188
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PIC32MX3XX/4XX
FIGURE 29-23: EJTAG TIMING CHARACTERISTICS
TTCKeye TTCKhigh TTCKlow Trf
TCK Trf TMS TDI TTsetup TThold TDO TRST* TTRST*low TTDOout TTDOzstate Trf Trf
Defined
Undefined
Trf
TABLE 29-41: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +105C for V-Temp Description(1) TCK Cycle Time TCK High Time TCK Low Time TAP Signals Setup Time Before Rising TCK TAP Signals Hold Time After Rising TCK TDO Output Delay Time from Falling TCK Min. 25 10 10 5 3 -- -- 25 -- Max. -- -- -- -- -- 5 5 -- -- Units ns ns ns ns ns ns ns ns ns Conditions -- -- -- -- -- -- -- -- --
Param. No. EJ1 EJ2 EJ3 EJ4 EJ5 EJ6 EJ7 EJ8 EJ9 Note 1:
Symbol TTCKCYC TTCKHIGH TTCKLOW TTSETUP TTHOLD TTDOOUT
TTDOZSTATE TDO 3-State Delay Time from Falling TCK TTRSTLOW TRF TRST Low Time TAP Signals Rise/Fall Time, All Input and Output
These parameters are characterized, but not tested in manufacturing.
(c) 2011 Microchip Technology Inc.
DS61143H-page 189
PIC32MX3XX/4XX
NOTES:
DS61143H-page 190
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
30.0
30.1
PACKAGING INFORMATION
Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC32MX360F 512H-80I/PT
e3
0510017
100-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
PIC32MX360F 256L-80I/PT
e3
0510017
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC32MX360F 512H-80I/MR
e3
0510017
121-Lead XBGA (10x10x1.1 mm)
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC32MX460F 512L-80I/BG
e3
0510017
Legend: XX...X Y YY WW NNN * Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2011 Microchip Technology Inc.
DS61143H-page 191
PIC32MX3XX/4XX
30.2 Package Details
The following sections give the technical details of the packages.
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DS61143H-page 192
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2011 Microchip Technology Inc.
DS61143H-page 193
PIC32MX3XX/4XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS61143H-page 194
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2011 Microchip Technology Inc.
DS61143H-page 195
PIC32MX3XX/4XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS61143H-page 196
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
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D D1
e E E1
b
N 1 23
NOTE 1 c
NOTE 2
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A2
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(c) 2011 Microchip Technology Inc.
DS61143H-page 197
PIC32MX3XX/4XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS61143H-page 198
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2011 Microchip Technology Inc.
DS61143H-page 199
PIC32MX3XX/4XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS61143H-page 200
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
(c) 2011 Microchip Technology Inc.
DS61143H-page 201
PIC32MX3XX/4XX
NOTES:
DS61143H-page 202
(c) 2011 Microchip Technology Inc.
PIC32MX3XX/4XX
APPENDIX A: REVISION HISTORY
Revision E (July 2008)
* Updated the PIC32MX340F128H features in Table 1 to include 4 programmable DMA channels.
Revision F (June 2009)
This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: * Changed all instances of OSCI to OSC1 and OSCO to OSC2 * Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE * Deleted registers in most sections, refer to the related section of the "PIC32 Family Reference Manual" (DS61132). The other changes are referenced by their respective section in the following table.
TABLE A-1:
MAJOR SECTION UPDATES
Update Description Added a "Packages" column to Table 1 and Table 2. Corrected all pin diagrams to update the following pin names. * * * * Changed PGC1/EMUC1 to PGEC1 Changed PGD1/EMUD1 to PGED1 Changed PGC2/EMUC2 to PGEC2 Changed PGD2/EMUD2 to PGED2
Section Name "High-Performance, General Purpose and USB 32-bit Flash Microcontrollers"
Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant. Added 64-Lead QFN package pin diagrams, one for General Purpose and one for USB. Section 1.0 "Device Overview" Section 2.0 "Guidelines for Getting Started with 32-bit Microcontrollers" Reconstructed Figure 1-1 to include Timers, ADC and RTCC in the block diagram. Added a new section to the data sheet that provides the following information: * * * * * * * Basic Connection Requirements Capacitors Master Clear Pin ICSPTM Pins External Oscillator Pins Configuration of Analog and Digital Pins Unused I/Os
Section 4.0 "Memory Organization"
Updated the memory maps, Figure 4-1 through Figure 4-6. All summary peripheral register maps were relocated to Section 4.0 "Memory Organization". Removed the "Address" column from Table 7-1. Added a second paragraph in Section 12.1.3 "Analog Inputs" to clarify that all pins that share ANx functions are analog by default, because the AD1PCFG register has a default value of 0x0000.
Section 7.0 "Interrupt Controller" Section 12.0 "I/O Ports"
(c) 2011 Microchip Technology Inc.
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TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
Update Description Section Name
Section 26.0 "Special Features" Modified bit names and locations in Register 26-5 "DEVID: Device and Revision ID Register". Replaced "TSTARTUP" with "TPU", and "64-ms nominal delay" with "TPWRT", in Section 26.3.1 "On-Chip Regulator and POR". The information that appeared in the Watchdog Timer and the Programming and Diagnostics sections of 61143E version of this data sheet has been incorporated into the Special Features section: * Section 26.2 "Watchdog Timer (WDT)" * Section 26.4 "Programming and Diagnostics" Section 29.0 "Electrical Characteristics" Added the 64-Lead QFN package to Table 29-3. Updated data in Table 29-5. Updated data in Table 29-7. Updated data in Table 29-4, Table 29-5, Table 29-7 and Table 29-8. Updated data in Table 29-11. Added OS42 parameter to Table 29-17. Replaced Table 29-23. Replaced Table 29-24. Replaced Table 29-25. Updated Table 29-36. Section 30.0 "Packaging Information" Added 64-Lead QFN package marking information to Section 30.1 "Package Marking Information". Added the 64-Lead QFN (MR) package drawing and land pattern to Section 30.2 "Package Details". "Product Identification System" Added the MR package designator for the 64-Lead (9x9x0.9) QFN.
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Revision G (April 2010)
The revision includes the following global update: * Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table.
TABLE A-2:
MAJOR SECTION UPDATES
Update Description
Section Name
"High-Performance, General Purpose Updated the crystal oscillator range to 3 MHz to 25 MHz (see Peripheral and USB 32-bit Flash Features:) Microcontrollers" Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table 1: "PIC32MX General Purpose - Features" and Table 2: "PIC32MX USB - Features" Added the following tables: - Table 3: "Pin Names: PIC32MX320F128L, PIC32MX340F128L, and PIC32MX360F128L, and PIC32MX360F512L Devices", - Table 4: "Pin Names: PIC32MX440F128L, PIC32MX460F256L and PIC32MX460F512L Devices" Updated the following pins as 5V tolerant: - 64-pin QFN (USB): Pin 34 (VBUS), Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP (USB): Pin 34 (Vbus), Pin 36 (D-/RG3), Pin 37 (D+/RG2) and Pin 42 (IC1/RTCC/INT1/RD8) - 100-pin TQFP (USB): Pin 54 (VBUS), Pin 56 (D-/RG3) and Pin 57 (D+/RG2) Section 1.0 "Device Overview" Section 2.0 "Guidelines for Getting Started with 32-bit Microcontrollers" Updated the Pinout I/O Descriptions table to include the device pin numbers (see Table 1-1) Updated the Ohm value for the low-ESR capacitor from less than 5 to less than 1 (see Section 2.3.1 "Internal Regulator Mode"). Labeled the capacitor on the VCAP/VDDCORE pin as CEFC in Figure 2-1. Changed 10 F capacitor to CEFC capacitor in Section 2.3 "Capacitor on Internal Voltage Regulator (VCAP/VCORE)". Section 4.0 "Memory Organization" Updated all register map tables to include the "All Resets" column. Separated the PORT register maps into individual tables (see Table 4-21 through Table 4-34). In addition, formatting changes were made to improve readability. Section 12.0 "I/O Ports" Section 22.0 "10-bit Analog-to-Digital Converter (ADC)" Section 26.0 "Special Features" Updated the second paragraph of Section 12.1.2 "Digital Inputs" and removed Table 12-1. Updated the ADC Conversion Clock Period Block Diagram (see Figure 222). Extensive updates were made to Section 26.2 "Watchdog Timer (WDT)" and Section 26.3 "On-Chip Voltage Regulator".
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TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
Update Description Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 29-3). Updated the conditions for parameters DC20, DC21, DC22 and DC23 in Table 29-5. Updated the comments for parameter D321 (CEFC) in Table 29-15. Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 29-13). Section 30.0 "Packaging Information" Added the 121-pin XBGA package marking information and package details. "Product Identification System" Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed. Section Name Section 29.0 "Electrical Characteristics"
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Revision H (May 2011)
The revision includes the following global update: * All references to VDDCORE/VCAP have been changed to: VCORE/VCAP * Added references to the new V-Temp temperature range: -40C to +105C This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table.
TABLE A-3:
MAJOR SECTION UPDATES
Section Name Update Description Updated the VBUS description in Table 1-1: "Pinout I/O Descriptions". Added Note 2 and changed the RIPL<2:0> bits to SRIPL<2:0> in the Interrupt Register Map tables (see Table 4-2 through Table 4-6. Added Note 2 to the Timer1-5 Register Map (see Table 4-7). Updated the All Resets value for I2C1CON<15:0> and I2C2CON<15:0> in the I2C1 and I2C2 Register Map (see Table 4-10). Updated the All Resets value for SPI1STAT<15:0> and SPI2STAT<15:0> in the SPI1 and SPI2 Register Map (see Table 4-12). Updated the All Resets value for CM1CON<15:0> and CM2CON<15:0> in the Comparator Register Map (see Table 4-17). Renamed the RCDIV<2:0> bits to FRCDIV<2:0> and the LOCK bit to SLOCK in the OSCCON register, and added Note 3 and the SYSKEYregister to the System Control Registers Map (see Table 4-20). Updated the All Resets value for the PMSTAT register in the Parallel Master Port Register Map (see Table 4-37). Updated the All Resets value for CHECON<15:0> and CHETAG<15:0> in the Prefetch Register Map (see Table 4-39). Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2 register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively in the Device Configuration Word Summary (see Table 4-41). Added Notes 1 through 4 to the USB Register Map (see Table 4-43).
Section 1.0 "Device Overview" Section 4.0 "Memory Organization"
Section 5.0 "Flash Program Memory" Section 8.0 "Oscillator Configuration" Section 11.0 "USB On-The-Go (OTG)" Section 16.0 "Output Compare" Section 22.0 "10-bit Analog-to-Digital Converter (ADC)" Section 26.0 "Special Features"
Added a note on Flash LVD Delay and Example 5-1. Updated the PIC32MX3XX/4XX Family Clock Diagram (see Figure 8-1). Updated the PIC32MX3XX/4XX Family USB Interface Diagram (see Figure 11-1). Updated the Output Compare Module Block Diagram (see Figure 16-1). Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2). Renamed FUPLLEN, FUPLLIDIV, and FPLLMULT in the DEVCFG2 register to: UPLLEN, UPLLIDIV, and FPLLMUL, respectively (see Register 26-3).
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PIC32MX3XX/4XX
TABLE A-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Section 29.0 "Electrical Characteristics" Update Description Added the new V-Temp temperature range (-40C to +105C) to the heading of all specification tables. Updated the Ambient temperature under bias, updated the Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added Voltage on VBUS with respect to Vss in Absolute Maximum Ratings. Added the characteristic, DC5a to Operating MIPS vs. Voltage (see Table 29-1). Updated or added the following parameters to the Operating Current (IDD) DC Characteristics: DC20, DC23, DC24c, DC25d, DC26c (see Table 29-5). Added the following parameters to the Idle Current (IIDLE) DC Characteristics: DC30c, DC31c, DC32c, DS33c, DC34c, DC35c, and DC36c (see Table 29-6). Added the following parameters to the Power-down Current (IPD) DC Characteristics: DC40g, DC40h, DC40i, DC41g, DC41h, DC42g, DC42h, DC42i, DC43h, and DC43i (see Table 29-7). Added the Brown-out Reset (BOR) Electrical Characteristics (see Table 29-10). Removed all Conditions from the Program Memory DC Characteristics (see Table 29-11). Removed the AC Characteristics voltage reference table (Table 29-15). Added Note 2 to the PLL Clock Timing Specifications (see Table 29-18). Updated the OC/PWM Module Timing Characteristics (see Figure 29-9). Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table 29-32). Added parameter numbers (AD13, AD14, and AD15) to the ADC Module Specifications (see Table 29-34). Updated the 10-bit ADC Conversion Rate Parameters (see Table 29-35). Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion Timing Requirements (see Table 29-36). Updated the Conditions for parameters USB313, USB318, and USB319 in the OTG Electrical Specifications (see Table 29-40). Section 30.0 "Packaging Information" Product Identification System Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) - 9x9x0.9 mm Body [QFN] packing diagram. Added the new V-Temp (V) temperature information.
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INDEX
A
AC Characteristics ............................................................ 161 Internal RC Accuracy ................................................ 163 AC Electrical Specifications Parallel Master Port Read Requirements ................. 186 Parallel Master Port Write Requirements.................. 187 Parallel Slave Port Requirements ............................. 185 Assembler MPASM Assembler................................................... 148
M
Microchip Internet Web Site.............................................. 209 MPLAB ASM30 Assembler, Linker, Librarian ................... 148 MPLAB Integrated Development Environment Software.. 147 MPLAB PM3 Device Programmer .................................... 150 MPLAB REAL ICE In-Circuit Emulator System ................ 149 MPLINK Object Linker/MPLIB Object Librarian ................ 148
P
Packaging ......................................................................... 191 Details....................................................................... 192 Marking..................................................................... 191 PIC32 Family USB Interface Diagram .............................. 100 Pinout I/O Descriptions (table)............................................ 22 Power-on Reset (POR) and On-Chip Voltage Regulator ............................... 138
B
Block Diagrams ADC Module.............................................................. 123 Comparator I/O Operating Modes............................. 125 Comparator Voltage Reference ................................ 127 Connections for On-Chip Voltage Regulator............. 138 Input Capture ............................................................ 107 JTAG Compliant Application Showing Daisy-Chaining of Components ........................ 139 Output Compare Module........................................... 109 Reset System.............................................................. 87 RTCC ........................................................................ 121 Type B Timer ................................................ 37, 95, 105 UART ........................................................................ 115 WDT.......................................................................... 137 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 138
R
Reader Response............................................................. 210
S
Serial Peripheral Interface (SPI) ... 87, 97, 111, 119, 121, 130 Software Simulator (MPLAB SIM) .................................... 149 Special Features............................................................... 131
T
Timer1 Module.............................................. 89, 95, 103, 105 Timing Diagrams 10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000) .. 183 10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)....................................... 184 I2Cx Bus Data (Master Mode) .................................. 175 I2Cx Bus Data (Slave Mode) .................................... 177 I2Cx Bus Start/Stop Bits (Master Mode)................... 175 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 177 Input Capture (CAPx) ............................................... 169 OC/PWM .................................................................. 170 Output Compare (OCx) ............................................ 169 Parallel Master Port Write................................. 186, 187 Parallel Slave Port .................................................... 185 SPIx Master Mode (CKE = 0) ................................... 171 SPIx Master Mode (CKE = 1) ................................... 172 SPIx Slave Mode (CKE = 0) ..................................... 173 SPIx Slave Mode (CKE = 1) ..................................... 174 Timer1, 2, 3, 4, 5 External Clock .............................. 167 Transmission (8-bit or 9-bit Data) ............................. 116 UART Reception with Receive Overrun ................... 117 Timing Requirements CLKO and I/O ........................................................... 164 Timing Specifications I2Cx Bus Data Requirements (Master Mode)........... 175 I2Cx Bus Data Requirements (Slave Mode)............. 178 Output Compare Requirements................................ 169 Simple OC/PWM Mode Requirements ..................... 170 SPIx Master Mode (CKE = 0) Requirements............ 171 SPIx Master Mode (CKE = 1) Requirements............ 172 SPIx Slave Mode (CKE = 1) Requirements.............. 174
C
C Compilers MPLAB C18 .............................................................. 148 Comparator Operation .................................................................. 126 Comparator Voltage Reference Configuring................................................................ 128 CPU Module.................................................................. 31, 37 Customer Change Notification Service ............................. 209 Customer Notification Service........................................... 209 Customer Support ............................................................. 209
D
DC Characteristics ............................................................ 152 I/O Pin Input Specifications....................................... 157 I/O Pin Output Specifications .................................... 158 Idle Current (IIDLE) .................................................... 154 Operating Current (IDD)............................................. 153 Power-Down Current (IPD) ........................................ 155 Program Memory ...................................................... 159 Temperature and Voltage Specifications .................. 152 Development Support ....................................................... 147
E
Electrical Characteristics................................................... 151 AC ............................................................................. 161 Errata .................................................................................. 19
F
Flash Program Memory ...................................................... 85 RTSP Operation.......................................................... 85
I
I/O Ports .................................................................... 101, 115 Parallel I/O (PIO)....................................................... 102 Internet Address................................................................ 209
V
VCORE/VCAP Pin ............................................................... 138 Voltage Reference Specifications..................................... 160 Voltage Regulator (On-Chip) ............................................ 138
(c) 2011 Microchip Technology Inc.
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PIC32MX3XX/4XX
W
Watchdog Timer Operation .................................................................. 137 WWW Address.................................................................. 209 WWW, On-Line Support...................................................... 19
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PIC32MX3XX/4XX
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions.
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PIC32MX3XX/4XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS61143H FAX: (______) _________ - _________
Device: PIC32MX3XX/4XX Questions: 1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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PIC32MX3XX/4XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 3XX F 512 H T - 80 I / PT - XXX Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern
Examples: PIC32MX320F032H-40I/PT: General purpose PIC32MX, 32 KB program memory, 64-pin, Industrial temperature, TQFP package. PIC32MX360F256L-80I/PT: General purpose PIC32MX, 256 KB program memory, 100-pin, Industrial temperature, TQFP package.
Flash Memory Family
Architecture Product Groups Flash Memory Family Program Memory Size MX = 32-bit RISC MCU core 3XX = General purpose microcontroller family 4XX = USB F 32 64 128 256 512 = Flash program memory = 32K = 64K = 128K = 256K = 512K
Speed
40 = 40 MHz 80 = 80 MHz H L I V PT PT MR BG = 64-pin = 100-pin = -40 C to +85 C (Industrial) = -40 C to +105 C (V-Temp) = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) = 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)
Pin Count
Temperature Range
Package
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample
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Worldwide Sales and Service
AMERICAS
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ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
05/02/11
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